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1/*
2 * Copyright 2008,2010 Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef _MMC_H_
11#define _MMC_H_
12
13#include <linux/list.h>
14#include <linux/compiler.h>
15#include <part.h>
16
17#define SAMPLE_STEP_COUNT 1
18#define SD_VERSION_SD 0x20000
19#define SD_VERSION_3 (SD_VERSION_SD | 0x300)
20#define SD_VERSION_2 (SD_VERSION_SD | 0x200)
21#define SD_VERSION_1_0 (SD_VERSION_SD | 0x100)
22#define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a)
23#define MMC_VERSION_MMC 0x10000
24#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
25#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102)
26#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104)
27#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202)
28#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300)
29#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400)
30#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401)
31#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402)
32#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403)
33#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429)
34#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
35#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500)
36#define MMC_VERSION_5_1 (MMC_VERSION_MMC | 0x501)
37
38#define MMC_MODE_HS (1 << 0)
39#define MMC_MODE_HS_52MHz (1 << 1)
40#define MMC_MODE_4BIT (1 << 2)
41#define MMC_MODE_8BIT (1 << 3)
42#define MMC_MODE_SPI (1 << 4)
43#define MMC_MODE_HC (1 << 5)
44#define MMC_MODE_DDR_52MHz (1 << 6)
45
46#define SD_DATA_4BIT 0x00040000
47
48#define IS_SD(x) (x->version & SD_VERSION_SD)
49
50#define MMC_DATA_READ 1
51#define MMC_DATA_WRITE 2
52
53#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
54#define UNUSABLE_ERR -17 /* Unusable Card */
55#define COMM_ERR -18 /* Communications Error */
56#define TIMEOUT -19
57#define IN_PROGRESS -20 /* operation is in progress */
58#define SWITCH_ERR -21 /* Card reports failure to switch mode */
59
60#define MMC_CMD_GO_IDLE_STATE 0
61#define MMC_CMD_SEND_OP_COND 1
62#define MMC_CMD_ALL_SEND_CID 2
63#define MMC_CMD_SET_RELATIVE_ADDR 3
64#define MMC_CMD_SET_DSR 4
65#define MMC_CMD_SWITCH 6
66#define MMC_CMD_SELECT_CARD 7
67#define MMC_CMD_SEND_EXT_CSD 8
68#define MMC_CMD_SEND_CSD 9
69#define MMC_CMD_SEND_CID 10
70#define MMC_CMD_STOP_TRANSMISSION 12
71#define MMC_CMD_SEND_STATUS 13
72#define MMC_CMD_SET_BLOCKLEN 16
73#define MMC_CMD_READ_SINGLE_BLOCK 17
74#define MMC_CMD_READ_MULTIPLE_BLOCK 18
75#define MMC_CMD_SET_BLOCK_COUNT 23
76#define MMC_CMD_WRITE_SINGLE_BLOCK 24
77#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
78#define MMC_CMD_SET_WRITE_PROTECT 28
79#define MMC_CMD_CLR_WRITE_PROT 29
80#define MMC_CMD_SEND_WRITE_PROT 30
81#define MMC_CMD_SEND_WRITE_PROT_TYPE 31
82#define MMC_CMD_ERASE_GROUP_START 35
83#define MMC_CMD_ERASE_GROUP_END 36
84#define MMC_CMD_ERASE 38
85#define MMC_CMD_APP_CMD 55
86#define MMC_CMD_SPI_READ_OCR 58
87#define MMC_CMD_SPI_CRC_ON_OFF 59
88#define MMC_CMD_RES_MAN 62
89
90#define MMC_CMD62_ARG1 0xefac62ec
91#define MMC_CMD62_ARG2 0xcbaea7
92
93
94#define SD_CMD_SEND_RELATIVE_ADDR 3
95#define SD_CMD_SWITCH_FUNC 6
96#define SD_CMD_SEND_IF_COND 8
97
98#define SD_CMD_APP_SET_BUS_WIDTH 6
99#define SD_CMD_ERASE_WR_BLK_START 32
100#define SD_CMD_ERASE_WR_BLK_END 33
101#define SD_CMD_APP_SEND_OP_COND 41
102#define SD_CMD_APP_SEND_SCR 51
103
104/* SCR definitions in different words */
105#define SD_HIGHSPEED_BUSY 0x00020000
106#define SD_HIGHSPEED_SUPPORTED 0x00020000
107
108#define OCR_BUSY 0x80000000
109#define OCR_HCS 0x40000000
110#define OCR_VOLTAGE_MASK 0x007FFF80
111#define OCR_ACCESS_MODE 0x60000000
112
113#define SECURE_ERASE 0x80000000
114
115#define MMC_STATUS_MASK (~0x0206BF7F)
116#define MMC_STATUS_SWITCH_ERROR (1 << 7)
117#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
118#define MMC_STATUS_CURR_STATE (0xf << 9)
119#define MMC_STATUS_ERROR (1 << 19)
120
121#define MMC_STATE_PRG (7 << 9)
122
123#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
124#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
125#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
126#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
127#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
128#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
129#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
130#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
131#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
132#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
133#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
134#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
135#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
136#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
137#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
138#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
139#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
140
141#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
142#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
143 addressed by index which are
144 1 in value field */
145#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
146 addressed by index, which are
147 1 in value field */
148#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
149
150#define SD_SWITCH_CHECK 0
151#define SD_SWITCH_SWITCH 1
152
153/*
154 * EXT_CSD fields
155 */
156
157
158#define EXT_CSD_CLASS_6_CTRL 59 /*R/W/E_P*/
159#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
160#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
161#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
162#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
163#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
164#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
165#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
166#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
167#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
168#define EXT_CSD_WR_REL_PARAM 166 /* R */
169#define EXT_CSD_WR_REL_SET 167 /* R/W */
170#define EXT_CSD_RPMB_MULT 168 /* RO */
171#define EXT_CSD_USER_WP 171 /* R/W */
172#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
173#define EXT_CSD_BOOT_BUS_WIDTH 177
174#define EXT_CSD_PART_CONF 179 /* R/W */
175#define EXT_CSD_BUS_WIDTH 183 /* R/W */
176#define EXT_CSD_HS_TIMING 185 /* R/W */
177#define EXT_CSD_REV 192 /* RO */
178#define EXT_CSD_CARD_TYPE 196 /* RO */
179#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
180#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
181#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
182#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
183#define EXT_CSD_BOOT_MULT 226 /* RO */
184#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
185#define EXT_CSD_SUPPORTED_MODES 493 /* RO */
186#define EXT_CSD_FW_VERSION 254 /* RO, 261:254 */
187#define EXT_CSD_FW_CFG 169 /* R/W */
188#define EXT_CSD_MODE_CFG 30 /* R/W */
189#define EXT_CSD_FFU_STATUS 26 /* RO */
190#define EXT_CSD_DEV_LIFETIME_EST_TYP_A 268 /* RO */
191#define EXT_CSD_DEV_LIFETIME_EST_TYP_B 269 /* RO */
192
193
194/*
195 * EXT_CSD field definitions
196 */
197#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
198#define EXT_CSD_CMD_SET_SECURE (1 << 1)
199#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
200
201#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
202#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
203#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
204#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
205#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
206 | EXT_CSD_CARD_TYPE_DDR_1_2V)
207
208#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
209 /* SDR mode @1.8V I/O */
210#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
211 /* SDR mode @1.2V I/O */
212#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
213 EXT_CSD_CARD_TYPE_HS200_1_2V)
214
215#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
216#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
217#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
218#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
219#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
220#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
221
222#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
223#define EXT_CSD_TIMING_HS 1 /* HS */
224#define EXT_CSD_TIMING_HS200 2 /* HS200 */
225
226#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
227#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
228#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
229#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
230
231#define EXT_CSD_BOOT_ACK(x) (x << 6)
232#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
233#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
234
235#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
236#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
237#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
238
239#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
240#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
241#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
242
243#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
244
245#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
246#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
247
248#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
249
250#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
251#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
252
253#define R1_ILLEGAL_COMMAND (1 << 22)
254#define R1_APP_CMD (1 << 5)
255
256
257#define MMC_RSP_PRESENT (1 << 0)
258#define MMC_RSP_136 (1 << 1) /* 136 bit response */
259#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
260#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
261#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
262
263#define MMC_RSP_NONE (0)
264#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
265#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
266 MMC_RSP_BUSY)
267#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
268#define MMC_RSP_R3 (MMC_RSP_PRESENT)
269#define MMC_RSP_R4 (MMC_RSP_PRESENT)
270#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
271#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
272#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
273
274
275
276#define MMCPART_NOAVAILABLE (0xff)
277#define PART_ACCESS_MASK (0x7)
278#define PART_SUPPORT (0x1)
279#define ENHNCD_SUPPORT (0x2)
280#define PART_ENH_ATTRIB (0x1f)
281/* Maximum block size for MMC */
282#define MMC_MAX_BLOCK_LEN 512
283
284/* The number of MMC physical partitions. These consist of:
285 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
286 */
287#define MMC_NUM_BOOT_PARTITION 2
288#define MMC_PART_RPMB 3 /* RPMB partition number */
289
290/*write protect*/
291#define US_PWR_WP_DIS_BIT 1<<3
292#define US_PERM_WP_DIS_BIT 1<<4
293#define WP_CLEAR_TYPE 0
294#define WP_POWER_ON_TYPE (1<<1)
295#define WP_TEMPORARY_TYPE 1
296#define WP_PERMANENT_TYPE ((1<<0)|(1<<1))
297#define WP_TYPE_MASK 3
298#define WP_ENABLE_MASK 7
299#define WP_TEMPORARY_EN_BIT 0
300#define WP_POWER_ON_EN_BIT (1<<0)
301#define WP_PERM_EN_BIT (1<<2)
302#define WP_GRP_SIZE_MASK 31
303
304
305/*MMC CLK*/
306#define MMC_HIGH_26_MAX_DTR 26000000
307#define MMC_HIGH_52_MAX_DTR 52000000
308#define MMC_HIGH_DDR_MAX_DTR 52000000
309#define MMC_HS200_MAX_DTR 200000000
310
311//#define MMC_CMD23
312//#define MMC_HS200_MODE
313//#define MMC_HS400_MODE
314
315struct mmc_cid {
316 unsigned long psn;
317 unsigned short oid;
318 unsigned char mid;
319 unsigned char prv;
320 unsigned char mdt;
321 char pnm[7];
322};
323
324struct mmc_cmd {
325 ushort cmdidx;
326 uint resp_type;
327 uint cmdarg;
328 uint response[4];
329};
330
331struct mmc_data {
332 union {
333 char *dest;
334 const char *src; /* src buffers don't get written to */
335 };
336 uint flags;
337 uint blocks;
338 uint blocksize;
339};
340
341/* forward decl. */
342struct mmc;
343
344struct mmc_ops {
345 int (*send_cmd)(struct mmc *mmc,
346 struct mmc_cmd *cmd, struct mmc_data *data);
347 void (*set_ios)(struct mmc *mmc);
348 int (*init)(struct mmc *mmc);
349 int (*getcd)(struct mmc *mmc);
350 int (*getwp)(struct mmc *mmc);
351 int (*calibration)(struct mmc *mmc);
352 int (*refix)(struct mmc *mmc);
353 int (*calc)(struct mmc *mmc);
354};
355
356struct mmc_config {
357 const char *name;
358 const struct mmc_ops *ops;
359 uint host_caps;
360 uint voltages;
361 uint f_min;
362 uint f_max;
363 uint b_max;
364 unsigned char part_type;
365};
366
367struct clock_lay_t {
368 /* source clk, 24Mhz, 1Ghz */
369 unsigned int source;
370 /* core clk, Hz */
371 unsigned int core;
372 /* core clk, Hz */
373 unsigned int old_core;
374 /* bus clk */
375 unsigned int sdclk;
376};
377
378/* todly in ns*/
379#define TODLY_MIN_NS (2)
380#define TODLY_MAX_NS (14)
381
382/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
383struct mmc {
384 struct list_head link;
385 const struct mmc_config *cfg; /* provided configuration */
386 struct clock_lay_t clk_lay;
387 uint version;
388 void *priv;
389 uint has_init;
390 int high_capacity;
391 uint bus_width;
392 uint clock;
393 uint card_caps;
394 uint ocr;
395 uint dsr;
396 uint dsr_imp;
397 uint scr[2];
398 uint csd[4];
399 uint cid[4];
400 ushort rca;
401 char part_config;
402 char part_num;
403 uint tran_speed;
404 u8 part_support;
405 u8 part_attr;
406 u8 wr_rel_set;
407 uint read_bl_len;
408 uint write_bl_len;
409 uint erase_grp_size;
410 uint dev_lifetime_est_typ_a;
411 uint dev_lifetime_est_typ_b;
412 u64 capacity;
413 u64 capacity_user;
414 u64 capacity_boot;
415 u64 capacity_rpmb;
416 u64 capacity_gp[4];
417 u64 boot_size;
418 block_dev_desc_t block_dev;
419 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
420 char init_in_progress; /* 1 if we have done mmc_start_init() */
421 char preinit; /* start init as early as possible */
422 uint op_cond_response; /* the response byte from the last op_cond */
423 int ddr_mode;
424 unsigned char calout[20][20];
425 int refix;
426 int fixdiv;
427 uint hc_wp_grp_size; /* in 512-byte sectors */
428};
429struct mmc_hwpart_conf {
430 struct {
431 uint enh_start; /* in 512-byte sectors */
432 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
433 unsigned wr_rel_change : 1;
434 unsigned wr_rel_set : 1;
435 } user;
436 struct {
437 uint size; /* in 512-byte sectors */
438 unsigned enhanced : 1;
439 unsigned wr_rel_change : 1;
440 unsigned wr_rel_set : 1;
441 } gp_part[4];
442};
443
444enum mmc_hwpart_conf_mode {
445 MMC_HWPART_CONF_CHECK,
446 MMC_HWPART_CONF_SET,
447 MMC_HWPART_CONF_COMPLETE,
448};
449
450int emmc_eyetest_log(struct mmc *mmc, u32 line);
451int aml_emmc_refix(struct mmc *mmc);
452ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst);
453int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value);
454void mmc_set_bus_width(struct mmc *mmc, uint width);
455int mmc_register(struct mmc *mmc);
456struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
457void mmc_destroy(struct mmc *mmc);
458int mmc_initialize(bd_t *bis);
459int get_boot_size(char *name, uint64_t* size);
460int mmc_init(struct mmc *mmc);
461int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
462void mmc_set_clock(struct mmc *mmc, uint clock);
463struct mmc *find_mmc_device(int dev_num);
464int mmc_set_dev(int dev_num);
465void print_mmc_devices(char separator);
466int get_mmc_num(void);
467int mmc_switch_part(int dev_num, unsigned int part_num);
468int mmc_getcd(struct mmc *mmc);
469int board_mmc_getcd(struct mmc *mmc);
470int mmc_getwp(struct mmc *mmc);
471int board_mmc_getwp(struct mmc *mmc);
472int mmc_set_dsr(struct mmc *mmc, u16 val);
473/* Function to change the size of boot partition and rpmb partitions */
474int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
475 unsigned long rpmbsize);
476/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
477int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
478/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
479int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
480/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
481int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
482/* Functions to read / write the RPMB partition */
483int mmc_rpmb_set_key(struct mmc *mmc, void *key);
484int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
485int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
486 unsigned short cnt, unsigned char *key);
487int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
488 unsigned short cnt, unsigned char *key);
489int mmc_hwpart_config(struct mmc *mmc,
490 const struct mmc_hwpart_conf *conf,
491 enum mmc_hwpart_conf_mode mode);
492int mmc_switch_partition(struct mmc* mmc, unsigned int part);
493/**
494 * Start device initialization and return immediately; it does not block on
495 * polling OCR (operation condition register) status. Then you should call
496 * mmc_init, which would block on polling OCR status and complete the device
497 * initializatin.
498 *
499 * @param mmc Pointer to a MMC device struct
500 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
501 */
502int mmc_start_init(struct mmc *mmc);
503
504/**
505 * Set preinit flag of mmc device.
506 *
507 * This will cause the device to be pre-inited during mmc_initialize(),
508 * which may save boot time if the device is not accessed until later.
509 * Some eMMC devices take 200-300ms to init, but unfortunately they
510 * must be sent a series of commands to even get them to start preparing
511 * for operation.
512 *
513 * @param mmc Pointer to a MMC device struct
514 * @param preinit preinit flag value
515 */
516void mmc_set_preinit(struct mmc *mmc, int preinit);
517
518//#ifdef MMC_HS400_MODE
519unsigned int aml_sd_emmc_clktest(struct mmc *mmc);
520void update_all_line_eyetest(struct mmc *mmc);
521//#endif
522
523#ifdef CONFIG_GENERIC_MMC
524#ifdef CONFIG_MMC_SPI
525#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
526#else
527#define mmc_host_is_spi(mmc) 0
528#endif
529struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
530#else
531int mmc_legacy_init(int verbose);
532#endif
533
534void board_mmc_power_init(void);
535int board_mmc_init(bd_t *bis);
536int cpu_mmc_init(bd_t *bis);
537int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
538int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data);
539int mmc_ffu_op(int dev, u64 ffu_ver, void *addr, u64 cnt);
540/* Set block count limit because of 16 bit register limit on some hardware*/
541#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
542#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
543#endif
544
545#endif /* _MMC_H_ */
546
generated by cgit at 2024-05-19 13:39:50 (GMT)