blob: 7fb71f721910853969380b6e341b94910d275100
1 | /* |
2 | * Marvell MMC/SD/SDIO driver |
3 | * |
4 | * (C) Copyright 2012 |
5 | * Marvell Semiconductor <www.marvell.com> |
6 | * Written-by: Maen Suleiman, Gerald Kerma |
7 | * |
8 | * SPDX-License-Identifier: GPL-2.0+ |
9 | */ |
10 | |
11 | #ifndef __MVEBU_MMC_H__ |
12 | #define __MVEBU_MMC_H__ |
13 | |
14 | /* needed for the mmc_cfg definition */ |
15 | #include <mmc.h> |
16 | |
17 | #define MMC_BLOCK_SIZE 512 |
18 | |
19 | /* |
20 | * Clock rates |
21 | */ |
22 | |
23 | #define MVEBU_MMC_CLOCKRATE_MAX 50000000 |
24 | #define MVEBU_MMC_BASE_DIV_MAX 0x7ff |
25 | #define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK |
26 | #define MVEBU_MMC_BASE_FAST_CLK_100 100000000 |
27 | #define MVEBU_MMC_BASE_FAST_CLK_200 200000000 |
28 | |
29 | /* SDIO register */ |
30 | #define SDIO_SYS_ADDR_LOW 0x000 |
31 | #define SDIO_SYS_ADDR_HI 0x004 |
32 | #define SDIO_BLK_SIZE 0x008 |
33 | #define SDIO_BLK_COUNT 0x00c |
34 | #define SDIO_ARG_LOW 0x010 |
35 | #define SDIO_ARG_HI 0x014 |
36 | #define SDIO_XFER_MODE 0x018 |
37 | #define SDIO_CMD 0x01c |
38 | #define SDIO_RSP(i) (0x020 + ((i)<<2)) |
39 | #define SDIO_RSP0 0x020 |
40 | #define SDIO_RSP1 0x024 |
41 | #define SDIO_RSP2 0x028 |
42 | #define SDIO_RSP3 0x02c |
43 | #define SDIO_RSP4 0x030 |
44 | #define SDIO_RSP5 0x034 |
45 | #define SDIO_RSP6 0x038 |
46 | #define SDIO_RSP7 0x03c |
47 | #define SDIO_BUF_DATA_PORT 0x040 |
48 | #define SDIO_RSVED 0x044 |
49 | #define SDIO_HW_STATE 0x048 |
50 | #define SDIO_PRESENT_STATE0 0x048 |
51 | #define SDIO_PRESENT_STATE1 0x04c |
52 | #define SDIO_HOST_CTRL 0x050 |
53 | #define SDIO_BLK_GAP_CTRL 0x054 |
54 | #define SDIO_CLK_CTRL 0x058 |
55 | #define SDIO_SW_RESET 0x05c |
56 | #define SDIO_NOR_INTR_STATUS 0x060 |
57 | #define SDIO_ERR_INTR_STATUS 0x064 |
58 | #define SDIO_NOR_STATUS_EN 0x068 |
59 | #define SDIO_ERR_STATUS_EN 0x06c |
60 | #define SDIO_NOR_INTR_EN 0x070 |
61 | #define SDIO_ERR_INTR_EN 0x074 |
62 | #define SDIO_AUTOCMD12_ERR_STATUS 0x078 |
63 | #define SDIO_CURR_BYTE_LEFT 0x07c |
64 | #define SDIO_CURR_BLK_LEFT 0x080 |
65 | #define SDIO_AUTOCMD12_ARG_LOW 0x084 |
66 | #define SDIO_AUTOCMD12_ARG_HI 0x088 |
67 | #define SDIO_AUTOCMD12_INDEX 0x08c |
68 | #define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2)) |
69 | #define SDIO_AUTO_RSP0 0x090 |
70 | #define SDIO_AUTO_RSP1 0x094 |
71 | #define SDIO_AUTO_RSP2 0x098 |
72 | #define SDIO_CLK_DIV 0x128 |
73 | |
74 | #define WINDOW_CTRL(i) (0x108 + ((i) << 3)) |
75 | #define WINDOW_BASE(i) (0x10c + ((i) << 3)) |
76 | |
77 | /* SDIO_PRESENT_STATE */ |
78 | #define CARD_BUSY (1 << 1) |
79 | #define CMD_INHIBIT (1 << 0) |
80 | #define CMD_TXACTIVE (1 << 8) |
81 | #define CMD_RXACTIVE (1 << 9) |
82 | #define CMD_FIFO_EMPTY (1 << 13) |
83 | #define CMD_AUTOCMD12ACTIVE (1 << 14) |
84 | #define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \ |
85 | CMD_RXACTIVE | \ |
86 | CMD_TXACTIVE | \ |
87 | CMD_INHIBIT | \ |
88 | CARD_BUSY) |
89 | |
90 | /* |
91 | * SDIO_CMD |
92 | */ |
93 | |
94 | #define SDIO_CMD_RSP_NONE (0 << 0) |
95 | #define SDIO_CMD_RSP_136 (1 << 0) |
96 | #define SDIO_CMD_RSP_48 (2 << 0) |
97 | #define SDIO_CMD_RSP_48BUSY (3 << 0) |
98 | |
99 | #define SDIO_CMD_CHECK_DATACRC16 (1 << 2) |
100 | #define SDIO_CMD_CHECK_CMDCRC (1 << 3) |
101 | #define SDIO_CMD_INDX_CHECK (1 << 4) |
102 | #define SDIO_CMD_DATA_PRESENT (1 << 5) |
103 | #define SDIO_UNEXPECTED_RESP (1 << 7) |
104 | |
105 | #define SDIO_CMD_INDEX(x) ((x) << 8) |
106 | |
107 | /* |
108 | * SDIO_XFER_MODE |
109 | */ |
110 | |
111 | #define SDIO_XFER_MODE_STOP_CLK (1 << 5) |
112 | #define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1) |
113 | #define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2) |
114 | #define SDIO_XFER_MODE_INT_CHK_EN (1 << 3) |
115 | #define SDIO_XFER_MODE_TO_HOST (1 << 4) |
116 | #define SDIO_XFER_MODE_DMA (0 << 6) |
117 | |
118 | /* |
119 | * SDIO_HOST_CTRL |
120 | */ |
121 | |
122 | #define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0) |
123 | |
124 | #define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1) |
125 | #define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1) |
126 | #define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1) |
127 | #define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1) |
128 | #define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1) |
129 | |
130 | #define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3) |
131 | #define SDIO_HOST_CTRL_LSB_FIRST (1 << 4) |
132 | #define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9) |
133 | #define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9) |
134 | #define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10) |
135 | |
136 | #define SDIO_HOST_CTRL_TMOUT_MAX 0xf |
137 | #define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11) |
138 | #define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11) |
139 | #define SDIO_HOST_CTRL_TMOUT_EN (1 << 15) |
140 | |
141 | /* |
142 | * SDIO_SW_RESET |
143 | */ |
144 | |
145 | #define SDIO_SW_RESET_NOW (1 << 8) |
146 | |
147 | /* |
148 | * Normal interrupt status bits |
149 | */ |
150 | |
151 | #define SDIO_NOR_ERROR (1 << 15) |
152 | #define SDIO_NOR_UNEXP_RSP (1 << 14) |
153 | #define SDIO_NOR_AUTOCMD12_DONE (1 << 13) |
154 | #define SDIO_NOR_SUSPEND_ON (1 << 12) |
155 | #define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11) |
156 | #define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10) |
157 | #define SDIO_NOR_READ_WAIT_ON (1 << 9) |
158 | #define SDIO_NOR_CARD_INT (1 << 8) |
159 | #define SDIO_NOR_READ_READY (1 << 5) |
160 | #define SDIO_NOR_WRITE_READY (1 << 4) |
161 | #define SDIO_NOR_DMA_INI (1 << 3) |
162 | #define SDIO_NOR_BLK_GAP_EVT (1 << 2) |
163 | #define SDIO_NOR_XFER_DONE (1 << 1) |
164 | #define SDIO_NOR_CMD_DONE (1 << 0) |
165 | |
166 | /* |
167 | * Error status bits |
168 | */ |
169 | |
170 | #define SDIO_ERR_CRC_STATUS (1 << 14) |
171 | #define SDIO_ERR_CRC_STARTBIT (1 << 13) |
172 | #define SDIO_ERR_CRC_ENDBIT (1 << 12) |
173 | #define SDIO_ERR_RESP_TBIT (1 << 11) |
174 | #define SDIO_ERR_XFER_SIZE (1 << 10) |
175 | #define SDIO_ERR_CMD_STARTBIT (1 << 9) |
176 | #define SDIO_ERR_AUTOCMD12 (1 << 8) |
177 | #define SDIO_ERR_DATA_ENDBIT (1 << 6) |
178 | #define SDIO_ERR_DATA_CRC (1 << 5) |
179 | #define SDIO_ERR_DATA_TIMEOUT (1 << 4) |
180 | #define SDIO_ERR_CMD_INDEX (1 << 3) |
181 | #define SDIO_ERR_CMD_ENDBIT (1 << 2) |
182 | #define SDIO_ERR_CMD_CRC (1 << 1) |
183 | #define SDIO_ERR_CMD_TIMEOUT (1 << 0) |
184 | /* enable all for polling */ |
185 | #define SDIO_POLL_MASK 0xffff |
186 | |
187 | /* |
188 | * CMD12 error status bits |
189 | */ |
190 | |
191 | #define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0) |
192 | #define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1) |
193 | #define SDIO_AUTOCMD12_ERR_CRC (1 << 2) |
194 | #define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3) |
195 | #define SDIO_AUTOCMD12_ERR_INDEX (1 << 4) |
196 | #define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5) |
197 | #define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6) |
198 | |
199 | #define MMC_RSP_PRESENT (1 << 0) |
200 | /* 136 bit response */ |
201 | #define MMC_RSP_136 (1 << 1) |
202 | /* expect valid crc */ |
203 | #define MMC_RSP_CRC (1 << 2) |
204 | /* card may send busy */ |
205 | #define MMC_RSP_BUSY (1 << 3) |
206 | /* response contains opcode */ |
207 | #define MMC_RSP_OPCODE (1 << 4) |
208 | |
209 | #define MMC_BUSMODE_OPENDRAIN 1 |
210 | #define MMC_BUSMODE_PUSHPULL 2 |
211 | |
212 | #define MMC_BUS_WIDTH_1 0 |
213 | #define MMC_BUS_WIDTH_4 2 |
214 | #define MMC_BUS_WIDTH_8 3 |
215 | |
216 | /* Can the host do 4 bit transfers */ |
217 | #define MMC_CAP_4_BIT_DATA (1 << 0) |
218 | /* Can do MMC high-speed timing */ |
219 | #define MMC_CAP_MMC_HIGHSPEED (1 << 1) |
220 | /* Can do SD high-speed timing */ |
221 | #define MMC_CAP_SD_HIGHSPEED (1 << 2) |
222 | /* Can signal pending SDIO IRQs */ |
223 | #define MMC_CAP_SDIO_IRQ (1 << 3) |
224 | /* Talks only SPI protocols */ |
225 | #define MMC_CAP_SPI (1 << 4) |
226 | /* Needs polling for card-detection */ |
227 | #define MMC_CAP_NEEDS_POLL (1 << 5) |
228 | /* Can the host do 8 bit transfers */ |
229 | #define MMC_CAP_8_BIT_DATA (1 << 6) |
230 | |
231 | /* Nonremovable e.g. eMMC */ |
232 | #define MMC_CAP_NONREMOVABLE (1 << 8) |
233 | /* Waits while card is busy */ |
234 | #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) |
235 | /* Allow erase/trim commands */ |
236 | #define MMC_CAP_ERASE (1 << 10) |
237 | /* can support DDR mode at 1.8V */ |
238 | #define MMC_CAP_1_8V_DDR (1 << 11) |
239 | /* can support DDR mode at 1.2V */ |
240 | #define MMC_CAP_1_2V_DDR (1 << 12) |
241 | /* Can power off after boot */ |
242 | #define MMC_CAP_POWER_OFF_CARD (1 << 13) |
243 | /* CMD14/CMD19 bus width ok */ |
244 | #define MMC_CAP_BUS_WIDTH_TEST (1 << 14) |
245 | /* Host supports UHS SDR12 mode */ |
246 | #define MMC_CAP_UHS_SDR12 (1 << 15) |
247 | /* Host supports UHS SDR25 mode */ |
248 | #define MMC_CAP_UHS_SDR25 (1 << 16) |
249 | /* Host supports UHS SDR50 mode */ |
250 | #define MMC_CAP_UHS_SDR50 (1 << 17) |
251 | /* Host supports UHS SDR104 mode */ |
252 | #define MMC_CAP_UHS_SDR104 (1 << 18) |
253 | /* Host supports UHS DDR50 mode */ |
254 | #define MMC_CAP_UHS_DDR50 (1 << 19) |
255 | /* Host supports Driver Type A */ |
256 | #define MMC_CAP_DRIVER_TYPE_A (1 << 23) |
257 | /* Host supports Driver Type C */ |
258 | #define MMC_CAP_DRIVER_TYPE_C (1 << 24) |
259 | /* Host supports Driver Type D */ |
260 | #define MMC_CAP_DRIVER_TYPE_D (1 << 25) |
261 | /* CMD23 supported. */ |
262 | #define MMC_CAP_CMD23 (1 << 30) |
263 | /* Hardware reset */ |
264 | #define MMC_CAP_HW_RESET (1 << 31) |
265 | |
266 | struct mvebu_mmc_cfg { |
267 | u32 mvebu_mmc_base; |
268 | u32 mvebu_mmc_clk; |
269 | u8 max_bus_width; |
270 | struct mmc_config cfg; |
271 | }; |
272 | |
273 | /* |
274 | * Functions prototypes |
275 | */ |
276 | |
277 | int mvebu_mmc_init(bd_t *bis); |
278 | |
279 | #endif /* __MVEBU_MMC_H__ */ |
280 |