blob: 0607379537d7ccf1038a0d322fdf29d95fbc0df4
1 | /* |
2 | * NS16550 Serial Port |
3 | * originally from linux source (arch/powerpc/boot/ns16550.h) |
4 | * |
5 | * Cleanup and unification |
6 | * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH |
7 | * |
8 | * modified slightly to |
9 | * have addresses as offsets from CONFIG_SYS_ISA_BASE |
10 | * added a few more definitions |
11 | * added prototypes for ns16550.c |
12 | * reduced no of com ports to 2 |
13 | * modifications (c) Rob Taylor, Flying Pig Systems. 2000. |
14 | * |
15 | * added support for port on 64-bit bus |
16 | * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems |
17 | */ |
18 | |
19 | /* |
20 | * Note that the following macro magic uses the fact that the compiler |
21 | * will not allocate storage for arrays of size 0 |
22 | */ |
23 | |
24 | #include <linux/types.h> |
25 | |
26 | #ifdef CONFIG_DM_SERIAL |
27 | /* |
28 | * For driver model we always use one byte per register, and sort out the |
29 | * differences in the driver |
30 | */ |
31 | #define CONFIG_SYS_NS16550_REG_SIZE (-1) |
32 | #endif |
33 | |
34 | #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) |
35 | #error "Please define NS16550 registers size." |
36 | #elif defined(CONFIG_SYS_NS16550_MEM32) |
37 | #define UART_REG(x) u32 x |
38 | #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) |
39 | #define UART_REG(x) \ |
40 | unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ |
41 | unsigned char x; |
42 | #elif (CONFIG_SYS_NS16550_REG_SIZE < 0) |
43 | #define UART_REG(x) \ |
44 | unsigned char x; \ |
45 | unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; |
46 | #endif |
47 | |
48 | /** |
49 | * struct ns16550_platdata - information about a NS16550 port |
50 | * |
51 | * @base: Base register address |
52 | * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) |
53 | * @clock: UART base clock speed in Hz |
54 | */ |
55 | struct ns16550_platdata { |
56 | unsigned long base; |
57 | int reg_shift; |
58 | int clock; |
59 | }; |
60 | |
61 | struct udevice; |
62 | |
63 | struct NS16550 { |
64 | UART_REG(rbr); /* 0 */ |
65 | UART_REG(ier); /* 1 */ |
66 | UART_REG(fcr); /* 2 */ |
67 | UART_REG(lcr); /* 3 */ |
68 | UART_REG(mcr); /* 4 */ |
69 | UART_REG(lsr); /* 5 */ |
70 | UART_REG(msr); /* 6 */ |
71 | UART_REG(spr); /* 7 */ |
72 | #ifdef CONFIG_SOC_DA8XX |
73 | UART_REG(reg8); /* 8 */ |
74 | UART_REG(reg9); /* 9 */ |
75 | UART_REG(revid1); /* A */ |
76 | UART_REG(revid2); /* B */ |
77 | UART_REG(pwr_mgmt); /* C */ |
78 | UART_REG(mdr1); /* D */ |
79 | #else |
80 | UART_REG(mdr1); /* 8 */ |
81 | UART_REG(reg9); /* 9 */ |
82 | UART_REG(regA); /* A */ |
83 | UART_REG(regB); /* B */ |
84 | UART_REG(regC); /* C */ |
85 | UART_REG(regD); /* D */ |
86 | UART_REG(regE); /* E */ |
87 | UART_REG(uasr); /* F */ |
88 | UART_REG(scr); /* 10*/ |
89 | UART_REG(ssr); /* 11*/ |
90 | #endif |
91 | #ifdef CONFIG_DM_SERIAL |
92 | struct ns16550_platdata *plat; |
93 | #endif |
94 | }; |
95 | |
96 | #define thr rbr |
97 | #define iir fcr |
98 | #define dll rbr |
99 | #define dlm ier |
100 | |
101 | typedef struct NS16550 *NS16550_t; |
102 | |
103 | /* |
104 | * These are the definitions for the FIFO Control Register |
105 | */ |
106 | #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ |
107 | #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ |
108 | #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ |
109 | #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ |
110 | #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ |
111 | #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ |
112 | #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ |
113 | #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ |
114 | #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ |
115 | |
116 | #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ |
117 | #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ |
118 | |
119 | /* |
120 | * These are the definitions for the Modem Control Register |
121 | */ |
122 | #define UART_MCR_DTR 0x01 /* DTR */ |
123 | #define UART_MCR_RTS 0x02 /* RTS */ |
124 | #define UART_MCR_OUT1 0x04 /* Out 1 */ |
125 | #define UART_MCR_OUT2 0x08 /* Out 2 */ |
126 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
127 | #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ |
128 | |
129 | #define UART_MCR_DMA_EN 0x04 |
130 | #define UART_MCR_TX_DFR 0x08 |
131 | |
132 | /* |
133 | * These are the definitions for the Line Control Register |
134 | * |
135 | * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting |
136 | * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. |
137 | */ |
138 | #define UART_LCR_WLS_MSK 0x03 /* character length select mask */ |
139 | #define UART_LCR_WLS_5 0x00 /* 5 bit character length */ |
140 | #define UART_LCR_WLS_6 0x01 /* 6 bit character length */ |
141 | #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ |
142 | #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ |
143 | #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ |
144 | #define UART_LCR_PEN 0x08 /* Parity eneble */ |
145 | #define UART_LCR_EPS 0x10 /* Even Parity Select */ |
146 | #define UART_LCR_STKP 0x20 /* Stick Parity */ |
147 | #define UART_LCR_SBRK 0x40 /* Set Break */ |
148 | #define UART_LCR_BKSE 0x80 /* Bank select enable */ |
149 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
150 | |
151 | /* |
152 | * These are the definitions for the Line Status Register |
153 | */ |
154 | #define UART_LSR_DR 0x01 /* Data ready */ |
155 | #define UART_LSR_OE 0x02 /* Overrun */ |
156 | #define UART_LSR_PE 0x04 /* Parity error */ |
157 | #define UART_LSR_FE 0x08 /* Framing error */ |
158 | #define UART_LSR_BI 0x10 /* Break */ |
159 | #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ |
160 | #define UART_LSR_TEMT 0x40 /* Xmitter empty */ |
161 | #define UART_LSR_ERR 0x80 /* Error */ |
162 | |
163 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
164 | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
165 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
166 | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
167 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
168 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
169 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
170 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
171 | |
172 | /* |
173 | * These are the definitions for the Interrupt Identification Register |
174 | */ |
175 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
176 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
177 | |
178 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
179 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
180 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
181 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
182 | |
183 | /* |
184 | * These are the definitions for the Interrupt Enable Register |
185 | */ |
186 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
187 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
188 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
189 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
190 | |
191 | /* useful defaults for LCR */ |
192 | #define UART_LCR_8N1 0x03 |
193 | |
194 | void NS16550_init(NS16550_t com_port, int baud_divisor); |
195 | void NS16550_putc(NS16550_t com_port, char c); |
196 | char NS16550_getc(NS16550_t com_port); |
197 | int NS16550_tstc(NS16550_t com_port); |
198 | void NS16550_reinit(NS16550_t com_port, int baud_divisor); |
199 | |
200 | /** |
201 | * ns16550_calc_divisor() - calculate the divisor given clock and baud rate |
202 | * |
203 | * Given the UART input clock and required baudrate, calculate the divisor |
204 | * that should be used. |
205 | * |
206 | * @port: UART port |
207 | * @clock: UART input clock speed in Hz |
208 | * @baudrate: Required baud rate |
209 | * @return baud rate divisor that should be used |
210 | */ |
211 | int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate); |
212 | |
213 | /** |
214 | * ns16550_serial_ofdata_to_platdata() - convert DT to platform data |
215 | * |
216 | * Decode a device tree node for an ns16550 device. This includes the |
217 | * register base address and register shift properties. The caller must set |
218 | * up the clock frequency. |
219 | * |
220 | * @dev: dev to decode platform data for |
221 | * @return: 0 if OK, -EINVAL on error |
222 | */ |
223 | int ns16550_serial_ofdata_to_platdata(struct udevice *dev); |
224 | |
225 | /** |
226 | * ns16550_serial_probe() - probe a serial port |
227 | * |
228 | * This sets up the serial port ready for use, except for the baud rate |
229 | * @return 0, or -ve on error |
230 | */ |
231 | int ns16550_serial_probe(struct udevice *dev); |
232 | |
233 | /** |
234 | * struct ns16550_serial_ops - ns16550 serial operations |
235 | * |
236 | * These should be used by the client driver for the driver's 'ops' member |
237 | */ |
238 | extern const struct dm_serial_ops ns16550_serial_ops; |
239 |