blob: aa4a0e9654dd6262839aec65df1d8fab08e16076
1 | /* |
2 | * Copyright 2011, Marvell Semiconductor Inc. |
3 | * Lei Wen <leiwen@marvell.com> |
4 | * |
5 | * SPDX-License-Identifier: GPL-2.0+ |
6 | * |
7 | * Back ported to the 8xx platform (from the 8260 platform) by |
8 | * Murray.Jensen@cmst.csiro.au, 27-Jan-01. |
9 | */ |
10 | #ifndef __SDHCI_HW_H |
11 | #define __SDHCI_HW_H |
12 | |
13 | #include <asm/io.h> |
14 | #include <mmc.h> |
15 | #include <fdtdec.h> |
16 | |
17 | /* |
18 | * Controller registers |
19 | */ |
20 | |
21 | #define SDHCI_DMA_ADDRESS 0x00 |
22 | |
23 | #define SDHCI_BLOCK_SIZE 0x04 |
24 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
25 | |
26 | #define SDHCI_BLOCK_COUNT 0x06 |
27 | |
28 | #define SDHCI_ARGUMENT 0x08 |
29 | |
30 | #define SDHCI_TRANSFER_MODE 0x0C |
31 | #define SDHCI_TRNS_DMA 0x01 |
32 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 |
33 | #define SDHCI_TRNS_ACMD12 0x04 |
34 | #define SDHCI_TRNS_READ 0x10 |
35 | #define SDHCI_TRNS_MULTI 0x20 |
36 | |
37 | #define SDHCI_COMMAND 0x0E |
38 | #define SDHCI_CMD_RESP_MASK 0x03 |
39 | #define SDHCI_CMD_CRC 0x08 |
40 | #define SDHCI_CMD_INDEX 0x10 |
41 | #define SDHCI_CMD_DATA 0x20 |
42 | #define SDHCI_CMD_ABORTCMD 0xC0 |
43 | |
44 | #define SDHCI_CMD_RESP_NONE 0x00 |
45 | #define SDHCI_CMD_RESP_LONG 0x01 |
46 | #define SDHCI_CMD_RESP_SHORT 0x02 |
47 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 |
48 | |
49 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) |
50 | #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) |
51 | |
52 | #define SDHCI_RESPONSE 0x10 |
53 | |
54 | #define SDHCI_BUFFER 0x20 |
55 | |
56 | #define SDHCI_PRESENT_STATE 0x24 |
57 | #define SDHCI_CMD_INHIBIT 0x00000001 |
58 | #define SDHCI_DATA_INHIBIT 0x00000002 |
59 | #define SDHCI_DOING_WRITE 0x00000100 |
60 | #define SDHCI_DOING_READ 0x00000200 |
61 | #define SDHCI_SPACE_AVAILABLE 0x00000400 |
62 | #define SDHCI_DATA_AVAILABLE 0x00000800 |
63 | #define SDHCI_CARD_PRESENT 0x00010000 |
64 | #define SDHCI_CARD_STATE_STABLE 0x00020000 |
65 | #define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000 |
66 | #define SDHCI_WRITE_PROTECT 0x00080000 |
67 | |
68 | #define SDHCI_HOST_CONTROL 0x28 |
69 | #define SDHCI_CTRL_LED 0x01 |
70 | #define SDHCI_CTRL_4BITBUS 0x02 |
71 | #define SDHCI_CTRL_HISPD 0x04 |
72 | #define SDHCI_CTRL_DMA_MASK 0x18 |
73 | #define SDHCI_CTRL_SDMA 0x00 |
74 | #define SDHCI_CTRL_ADMA1 0x08 |
75 | #define SDHCI_CTRL_ADMA32 0x10 |
76 | #define SDHCI_CTRL_ADMA64 0x18 |
77 | #define SDHCI_CTRL_8BITBUS 0x20 |
78 | #define SDHCI_CTRL_CD_TEST_INS 0x40 |
79 | #define SDHCI_CTRL_CD_TEST 0x80 |
80 | |
81 | #define SDHCI_POWER_CONTROL 0x29 |
82 | #define SDHCI_POWER_ON 0x01 |
83 | #define SDHCI_POWER_180 0x0A |
84 | #define SDHCI_POWER_300 0x0C |
85 | #define SDHCI_POWER_330 0x0E |
86 | |
87 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A |
88 | |
89 | #define SDHCI_WAKE_UP_CONTROL 0x2B |
90 | #define SDHCI_WAKE_ON_INT 0x01 |
91 | #define SDHCI_WAKE_ON_INSERT 0x02 |
92 | #define SDHCI_WAKE_ON_REMOVE 0x04 |
93 | |
94 | #define SDHCI_CLOCK_CONTROL 0x2C |
95 | #define SDHCI_DIVIDER_SHIFT 8 |
96 | #define SDHCI_DIVIDER_HI_SHIFT 6 |
97 | #define SDHCI_DIV_MASK 0xFF |
98 | #define SDHCI_DIV_MASK_LEN 8 |
99 | #define SDHCI_DIV_HI_MASK 0x300 |
100 | #define SDHCI_CLOCK_CARD_EN 0x0004 |
101 | #define SDHCI_CLOCK_INT_STABLE 0x0002 |
102 | #define SDHCI_CLOCK_INT_EN 0x0001 |
103 | |
104 | #define SDHCI_TIMEOUT_CONTROL 0x2E |
105 | |
106 | #define SDHCI_SOFTWARE_RESET 0x2F |
107 | #define SDHCI_RESET_ALL 0x01 |
108 | #define SDHCI_RESET_CMD 0x02 |
109 | #define SDHCI_RESET_DATA 0x04 |
110 | |
111 | #define SDHCI_INT_STATUS 0x30 |
112 | #define SDHCI_INT_ENABLE 0x34 |
113 | #define SDHCI_SIGNAL_ENABLE 0x38 |
114 | #define SDHCI_INT_RESPONSE 0x00000001 |
115 | #define SDHCI_INT_DATA_END 0x00000002 |
116 | #define SDHCI_INT_DMA_END 0x00000008 |
117 | #define SDHCI_INT_SPACE_AVAIL 0x00000010 |
118 | #define SDHCI_INT_DATA_AVAIL 0x00000020 |
119 | #define SDHCI_INT_CARD_INSERT 0x00000040 |
120 | #define SDHCI_INT_CARD_REMOVE 0x00000080 |
121 | #define SDHCI_INT_CARD_INT 0x00000100 |
122 | #define SDHCI_INT_ERROR 0x00008000 |
123 | #define SDHCI_INT_TIMEOUT 0x00010000 |
124 | #define SDHCI_INT_CRC 0x00020000 |
125 | #define SDHCI_INT_END_BIT 0x00040000 |
126 | #define SDHCI_INT_INDEX 0x00080000 |
127 | #define SDHCI_INT_DATA_TIMEOUT 0x00100000 |
128 | #define SDHCI_INT_DATA_CRC 0x00200000 |
129 | #define SDHCI_INT_DATA_END_BIT 0x00400000 |
130 | #define SDHCI_INT_BUS_POWER 0x00800000 |
131 | #define SDHCI_INT_ACMD12ERR 0x01000000 |
132 | #define SDHCI_INT_ADMA_ERROR 0x02000000 |
133 | |
134 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF |
135 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 |
136 | |
137 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ |
138 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) |
139 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ |
140 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ |
141 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ |
142 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) |
143 | #define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
144 | |
145 | #define SDHCI_ACMD12_ERR 0x3C |
146 | |
147 | /* 3E-3F reserved */ |
148 | |
149 | #define SDHCI_CAPABILITIES 0x40 |
150 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
151 | #define SDHCI_TIMEOUT_CLK_SHIFT 0 |
152 | #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 |
153 | #define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
154 | #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 |
155 | #define SDHCI_CLOCK_BASE_SHIFT 8 |
156 | #define SDHCI_MAX_BLOCK_MASK 0x00030000 |
157 | #define SDHCI_MAX_BLOCK_SHIFT 16 |
158 | #define SDHCI_CAN_DO_8BIT 0x00040000 |
159 | #define SDHCI_CAN_DO_ADMA2 0x00080000 |
160 | #define SDHCI_CAN_DO_ADMA1 0x00100000 |
161 | #define SDHCI_CAN_DO_HISPD 0x00200000 |
162 | #define SDHCI_CAN_DO_SDMA 0x00400000 |
163 | #define SDHCI_CAN_VDD_330 0x01000000 |
164 | #define SDHCI_CAN_VDD_300 0x02000000 |
165 | #define SDHCI_CAN_VDD_180 0x04000000 |
166 | #define SDHCI_CAN_64BIT 0x10000000 |
167 | |
168 | #define SDHCI_CAPABILITIES_1 0x44 |
169 | |
170 | #define SDHCI_MAX_CURRENT 0x48 |
171 | |
172 | /* 4C-4F reserved for more max current */ |
173 | |
174 | #define SDHCI_SET_ACMD12_ERROR 0x50 |
175 | #define SDHCI_SET_INT_ERROR 0x52 |
176 | |
177 | #define SDHCI_ADMA_ERROR 0x54 |
178 | |
179 | /* 55-57 reserved */ |
180 | |
181 | #define SDHCI_ADMA_ADDRESS 0x58 |
182 | |
183 | /* 60-FB reserved */ |
184 | |
185 | #define SDHCI_SLOT_INT_STATUS 0xFC |
186 | |
187 | #define SDHCI_HOST_VERSION 0xFE |
188 | #define SDHCI_VENDOR_VER_MASK 0xFF00 |
189 | #define SDHCI_VENDOR_VER_SHIFT 8 |
190 | #define SDHCI_SPEC_VER_MASK 0x00FF |
191 | #define SDHCI_SPEC_VER_SHIFT 0 |
192 | #define SDHCI_SPEC_100 0 |
193 | #define SDHCI_SPEC_200 1 |
194 | #define SDHCI_SPEC_300 2 |
195 | |
196 | #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK) |
197 | |
198 | /* |
199 | * End of controller registers. |
200 | */ |
201 | |
202 | #define SDHCI_MAX_DIV_SPEC_200 256 |
203 | #define SDHCI_MAX_DIV_SPEC_300 2046 |
204 | |
205 | /* |
206 | * quirks |
207 | */ |
208 | #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) |
209 | #define SDHCI_QUIRK_REG32_RW (1 << 1) |
210 | #define SDHCI_QUIRK_BROKEN_R1B (1 << 2) |
211 | #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) |
212 | #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) |
213 | #define SDHCI_QUIRK_NO_CD (1 << 5) |
214 | #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) |
215 | #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7) |
216 | #define SDHCI_QUIRK_USE_WIDE8 (1 << 8) |
217 | |
218 | /* to make gcc happy */ |
219 | struct sdhci_host; |
220 | |
221 | /* |
222 | * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. |
223 | */ |
224 | #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) |
225 | #define SDHCI_DEFAULT_BOUNDARY_ARG (7) |
226 | struct sdhci_ops { |
227 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
228 | u32 (*read_l)(struct sdhci_host *host, int reg); |
229 | u16 (*read_w)(struct sdhci_host *host, int reg); |
230 | u8 (*read_b)(struct sdhci_host *host, int reg); |
231 | void (*write_l)(struct sdhci_host *host, u32 val, int reg); |
232 | void (*write_w)(struct sdhci_host *host, u16 val, int reg); |
233 | void (*write_b)(struct sdhci_host *host, u8 val, int reg); |
234 | #endif |
235 | }; |
236 | |
237 | struct sdhci_host { |
238 | char *name; |
239 | void *ioaddr; |
240 | unsigned int quirks; |
241 | unsigned int host_caps; |
242 | unsigned int version; |
243 | unsigned int clock; |
244 | struct mmc *mmc; |
245 | const struct sdhci_ops *ops; |
246 | int index; |
247 | |
248 | int bus_width; |
249 | struct fdt_gpio_state pwr_gpio; /* Power GPIO */ |
250 | struct fdt_gpio_state cd_gpio; /* Card Detect GPIO */ |
251 | |
252 | void (*set_control_reg)(struct sdhci_host *host); |
253 | void (*set_clock)(int dev_index, unsigned int div); |
254 | uint voltages; |
255 | |
256 | struct mmc_config cfg; |
257 | }; |
258 | |
259 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
260 | |
261 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
262 | { |
263 | if (unlikely(host->ops->write_l)) |
264 | host->ops->write_l(host, val, reg); |
265 | else |
266 | writel(val, host->ioaddr + reg); |
267 | } |
268 | |
269 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
270 | { |
271 | if (unlikely(host->ops->write_w)) |
272 | host->ops->write_w(host, val, reg); |
273 | else |
274 | writew(val, host->ioaddr + reg); |
275 | } |
276 | |
277 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
278 | { |
279 | if (unlikely(host->ops->write_b)) |
280 | host->ops->write_b(host, val, reg); |
281 | else |
282 | writeb(val, host->ioaddr + reg); |
283 | } |
284 | |
285 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
286 | { |
287 | if (unlikely(host->ops->read_l)) |
288 | return host->ops->read_l(host, reg); |
289 | else |
290 | return readl(host->ioaddr + reg); |
291 | } |
292 | |
293 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
294 | { |
295 | if (unlikely(host->ops->read_w)) |
296 | return host->ops->read_w(host, reg); |
297 | else |
298 | return readw(host->ioaddr + reg); |
299 | } |
300 | |
301 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
302 | { |
303 | if (unlikely(host->ops->read_b)) |
304 | return host->ops->read_b(host, reg); |
305 | else |
306 | return readb(host->ioaddr + reg); |
307 | } |
308 | |
309 | #else |
310 | |
311 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
312 | { |
313 | writel(val, host->ioaddr + reg); |
314 | } |
315 | |
316 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
317 | { |
318 | writew(val, host->ioaddr + reg); |
319 | } |
320 | |
321 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
322 | { |
323 | writeb(val, host->ioaddr + reg); |
324 | } |
325 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
326 | { |
327 | return readl(host->ioaddr + reg); |
328 | } |
329 | |
330 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
331 | { |
332 | return readw(host->ioaddr + reg); |
333 | } |
334 | |
335 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
336 | { |
337 | return readb(host->ioaddr + reg); |
338 | } |
339 | #endif |
340 | |
341 | int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk); |
342 | #endif /* __SDHCI_HW_H */ |
343 |