author | Edward Ho <edward.ho@amlogic.com> | 2019-06-19 09:28:01 (GMT) |
---|---|---|
committer | Edward Ho <edward.ho@amlogic.com> | 2019-06-20 02:48:06 (GMT) |
commit | 54f78f113a32df9c1fba89fdb49c7d48ab8d1743 (patch) | |
tree | d64c7077602978c7745a94227687b4d3bab1a731 | |
parent | c04dea725628fc5129ca510170d4f398e15571c3 (diff) | |
download | uboot-54f78f113a32df9c1fba89fdb49c7d48ab8d1743.zip uboot-54f78f113a32df9c1fba89fdb49c7d48ab8d1743.tar.gz uboot-54f78f113a32df9c1fba89fdb49c7d48ab8d1743.tar.bz2 |
[Sabrina] GPIO input function [2/2]
PD#SWPL-10039
Problem:
Modify the following pins to GPIO input
1. GPIOZ_3 (HW_ID_2)
2. GPIOZ_7 (HW_ID_0)
3. GPIOZ_8 (HW_ID_1)
4. GPIOAO_10 (FDR_L)
Solution:
GPIO
Verify:
sabrina
Change-Id: I12dd82d5b12630aeecfdfcebc7b29b9b6be40240
Signed-off-by: Edward Ho <edward.ho@amlogic.com>
-rwxr-xr-x | board/amlogic/sm1_sabrina_v1/firmware/timing.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/board/amlogic/sm1_sabrina_v1/firmware/timing.c b/board/amlogic/sm1_sabrina_v1/firmware/timing.c index 56ec691..5fbed33 100755 --- a/board/amlogic/sm1_sabrina_v1/firmware/timing.c +++ b/board/amlogic/sm1_sabrina_v1/firmware/timing.c @@ -664,4 +664,16 @@ bl2_reg_t __bl2_reg[] = { /* Init sys led*/ {AO_GPIO_O_EN_N, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0}, {AO_GPIO_O, (1 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0}, + + /* GPIO inputs */ + /* Disable Pull_UP_EN */ + {PAD_PULL_UP_EN_REG4, 0, ((1<< 8)| (1 << 7)| (1 << 3)), 0, BL2_INIT_STAGE_1, 0}, /* [3] GPIOZ_3; [7] GPIOZ_7; [8] GPIOZ_8 */ + {AO_RTI_PULL_UP_EN_REG, 0, (1<< 10), 0, BL2_INIT_STAGE_1, 0}, /* [10] GPIOAO_10 */ + /* Set the GPIO direction to Input */ + {PREG_PAD_GPIO4_EN_N, ((1<< 8)| (1 << 7)| (1 << 3)), ((1<< 8)| (1 << 7)| (1 << 3)), 0, BL2_INIT_STAGE_1, 0}, /* [3] GPIOZ_3; [7] GPIOZ_7; [8] GPIOZ_8 */ + {AO_GPIO_O_EN_N, (1 << 10), (1 << 10), 0, BL2_INIT_STAGE_1, 0}, /* [10] GPIOAO_10 */ + /* Set the pinmux to GPIO */ + {PERIPHS_PIN_MUX_6, 0, ((0xf<< 12)| (0xf <<28)), 0, BL2_INIT_STAGE_1, 0}, /* [15:12] GPIOZ_3; [31:28] GPIOZ_7 */ + {PERIPHS_PIN_MUX_7, 0, 0xf, 0, BL2_INIT_STAGE_1, 0}, /* [3:0] GPIOAO_10 */ + {AO_RTI_PINMUX_REG1, 0, (0xf << 8), 0, BL2_INIT_STAGE_1, 0}, /* [11:8] GPIOAO_10 */ }; |