| author | Xindong Xu <xindong.xu@amlogic.com> | 2019-11-28 01:34:41 (GMT) |
|---|---|---|
| committer | Gerrit Code Review <gituser@aml-code-master.amlogic.com> | 2019-11-28 01:34:41 (GMT) |
| commit | 5eca6fba372f4028cdb7c632c6ca5bf2da859610 (patch) | |
| tree | 2540e9d7202d7d8d265a9e7f139d30f40ee9ff96 | |
| parent | e464c3c3db46f9af3bf0655d09957869a34b7547 (diff) | |
| parent | c2ce2da3594e71a1f631bd0439c5e455875e74a3 (diff) | |
| download | uboot-5eca6fba372f4028cdb7c632c6ca5bf2da859610.zip uboot-5eca6fba372f4028cdb7c632c6ca5bf2da859610.tar.gz uboot-5eca6fba372f4028cdb7c632c6ca5bf2da859610.tar.bz2 | |
Merge "ddr: timing:LPDDR4_PHY_V_0_1_21 at G12A/G12B/TL1/TM2/A1/C1 bl33_v2015 [2/4]" into amlogic-dev-ref
39 files changed, 1350 insertions, 1046 deletions
diff --git a/arch/arm/cpu/armv8/g12a/firmware/acs/acs.c b/arch/arm/cpu/armv8/g12a/firmware/acs/acs.c index 66bd216..1d62808 100644 --- a/arch/arm/cpu/armv8/g12a/firmware/acs/acs.c +++ b/arch/arm/cpu/armv8/g12a/firmware/acs/acs.c @@ -59,4 +59,7 @@ acs_set_t __acs_set={ .rsv_set_version= 1, .rsv_set_length = 0, .rsv_set_addr = 0, + .board_id = {0,}, + .ddr_struct_size = {0,}, + .ddr_struct_org_size = sizeof(ddr_set_t), }; diff --git a/arch/arm/cpu/armv8/g12a/firmware/acs/acs.ld.S b/arch/arm/cpu/armv8/g12a/firmware/acs/acs.ld.S index cee812b..7c83e83 100644 --- a/arch/arm/cpu/armv8/g12a/firmware/acs/acs.ld.S +++ b/arch/arm/cpu/armv8/g12a/firmware/acs/acs.ld.S @@ -34,5 +34,5 @@ SECTIONS *(.data*) } - ASSERT(. <= 0xFFFB0000, "timing image has exceeded its limit.") + //ASSERT(. <= 0xFFFB0000, "timing image has exceeded its limit.") } diff --git a/arch/arm/cpu/armv8/g12a/firmware/acs/acs_entry.S b/arch/arm/cpu/armv8/g12a/firmware/acs/acs_entry.S index ec5f77e..fced848 100644 --- a/arch/arm/cpu/armv8/g12a/firmware/acs/acs_entry.S +++ b/arch/arm/cpu/armv8/g12a/firmware/acs/acs_entry.S @@ -26,7 +26,9 @@ acs_entry: .word __acs_set #ifdef CONFIG_MDUMP_COMPRESS .word __ramdump_data + .word __ddr_setting #else .word 0x0 + .word __ddr_setting #endif diff --git a/arch/arm/cpu/armv8/g12b/firmware/acs/acs.c b/arch/arm/cpu/armv8/g12b/firmware/acs/acs.c index 66bd216..1d62808 100644 --- a/arch/arm/cpu/armv8/g12b/firmware/acs/acs.c +++ b/arch/arm/cpu/armv8/g12b/firmware/acs/acs.c @@ -59,4 +59,7 @@ acs_set_t __acs_set={ .rsv_set_version= 1, .rsv_set_length = 0, .rsv_set_addr = 0, + .board_id = {0,}, + .ddr_struct_size = {0,}, + .ddr_struct_org_size = sizeof(ddr_set_t), }; diff --git a/arch/arm/cpu/armv8/g12b/firmware/acs/acs.ld.S b/arch/arm/cpu/armv8/g12b/firmware/acs/acs.ld.S index cee812b..7c83e83 100644 --- a/arch/arm/cpu/armv8/g12b/firmware/acs/acs.ld.S +++ b/arch/arm/cpu/armv8/g12b/firmware/acs/acs.ld.S @@ -34,5 +34,5 @@ SECTIONS *(.data*) } - ASSERT(. <= 0xFFFB0000, "timing image has exceeded its limit.") + //ASSERT(. <= 0xFFFB0000, "timing image has exceeded its limit.") } diff --git a/arch/arm/cpu/armv8/g12b/firmware/acs/acs_entry.S b/arch/arm/cpu/armv8/g12b/firmware/acs/acs_entry.S index d8c09d4..131ce57 100644 --- a/arch/arm/cpu/armv8/g12b/firmware/acs/acs_entry.S +++ b/arch/arm/cpu/armv8/g12b/firmware/acs/acs_entry.S @@ -26,6 +26,8 @@ acs_entry: .word __acs_set #ifdef CONFIG_MDUMP_COMPRESS .word __ramdump_data + .word __ddr_setting #else .word 0x0 + .word __ddr_setting #endif
\ No newline at end of file diff --git a/arch/arm/cpu/armv8/tl1/firmware/acs/acs.c b/arch/arm/cpu/armv8/tl1/firmware/acs/acs.c index 66bd216..1d62808 100644 --- a/arch/arm/cpu/armv8/tl1/firmware/acs/acs.c +++ b/arch/arm/cpu/armv8/tl1/firmware/acs/acs.c @@ -59,4 +59,7 @@ acs_set_t __acs_set={ .rsv_set_version= 1, .rsv_set_length = 0, .rsv_set_addr = 0, + .board_id = {0,}, + .ddr_struct_size = {0,}, + .ddr_struct_org_size = sizeof(ddr_set_t), }; diff --git a/arch/arm/cpu/armv8/tl1/firmware/acs/acs.ld.S b/arch/arm/cpu/armv8/tl1/firmware/acs/acs.ld.S index 03e0d80..d42918e 100644 --- a/arch/arm/cpu/armv8/tl1/firmware/acs/acs.ld.S +++ b/arch/arm/cpu/armv8/tl1/firmware/acs/acs.ld.S @@ -34,5 +34,5 @@ SECTIONS *(.data*) } - ASSERT(. <= 0xFFFC0000, "timing image has exceeded its limit.") + //ASSERT(. <= 0xFFFC0000, "timing image has exceeded its limit.") } diff --git a/arch/arm/cpu/armv8/tl1/firmware/acs/acs_entry.S b/arch/arm/cpu/armv8/tl1/firmware/acs/acs_entry.S index ec5f77e..fced848 100644 --- a/arch/arm/cpu/armv8/tl1/firmware/acs/acs_entry.S +++ b/arch/arm/cpu/armv8/tl1/firmware/acs/acs_entry.S @@ -26,7 +26,9 @@ acs_entry: .word __acs_set #ifdef CONFIG_MDUMP_COMPRESS .word __ramdump_data + .word __ddr_setting #else .word 0x0 + .word __ddr_setting #endif diff --git a/arch/arm/cpu/armv8/tm2/firmware/acs/acs.c b/arch/arm/cpu/armv8/tm2/firmware/acs/acs.c index 66bd216..1d62808 100644 --- a/arch/arm/cpu/armv8/tm2/firmware/acs/acs.c +++ b/arch/arm/cpu/armv8/tm2/firmware/acs/acs.c @@ -59,4 +59,7 @@ acs_set_t __acs_set={ .rsv_set_version= 1, .rsv_set_length = 0, .rsv_set_addr = 0, + .board_id = {0,}, + .ddr_struct_size = {0,}, + .ddr_struct_org_size = sizeof(ddr_set_t), }; diff --git a/arch/arm/cpu/armv8/tm2/firmware/acs/acs.ld.S b/arch/arm/cpu/armv8/tm2/firmware/acs/acs.ld.S index c91f5fa..d4cab43 100644 --- a/arch/arm/cpu/armv8/tm2/firmware/acs/acs.ld.S +++ b/arch/arm/cpu/armv8/tm2/firmware/acs/acs.ld.S @@ -14,5 +14,5 @@ SECTIONS *(.data*) } - ASSERT(. <= 0xFFFC0000, "timing image has exceeded its limit.") + //ASSERT(. <= 0xFFFC0000, "timing image has exceeded its limit.") } diff --git a/arch/arm/cpu/armv8/tm2/firmware/acs/acs_entry.S b/arch/arm/cpu/armv8/tm2/firmware/acs/acs_entry.S index 3919413..feca813 100644 --- a/arch/arm/cpu/armv8/tm2/firmware/acs/acs_entry.S +++ b/arch/arm/cpu/armv8/tm2/firmware/acs/acs_entry.S @@ -6,7 +6,9 @@ acs_entry: .word __acs_set #ifdef CONFIG_MDUMP_COMPRESS .word __ramdump_data + .word __ddr_setting #else .word 0x0 + .word __ddr_setting #endif diff --git a/arch/arm/include/asm/arch-g12a/acs.h b/arch/arm/include/asm/arch-g12a/acs.h index c65c647..bc35366 100644 --- a/arch/arm/include/asm/arch-g12a/acs.h +++ b/arch/arm/include/asm/arch-g12a/acs.h @@ -59,6 +59,9 @@ typedef struct acs_setting{ unsigned char rsv_set_version; unsigned short rsv_set_length; unsigned long rsv_set_addr; + char board_id[12]; + unsigned short ddr_struct_size[12]; + unsigned long ddr_struct_org_size; }__attribute__ ((packed)) acs_set_t; #endif diff --git a/arch/arm/include/asm/arch-g12a/ddr_define.h b/arch/arm/include/asm/arch-g12a/ddr_define.h index c52235c..b9a0dda 100644 --- a/arch/arm/include/asm/arch-g12a/ddr_define.h +++ b/arch/arm/include/asm/arch-g12a/ddr_define.h @@ -262,6 +262,7 @@ #endif #define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30) #define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29) +#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28) #define DDR_FUNC (DDR_FUNC_D2PLL | \ DDR_FUNC_LP | \ DDR_FUNC_ZQ_PD | \ diff --git a/arch/arm/include/asm/arch-g12a/timing.h b/arch/arm/include/asm/arch-g12a/timing.h index 6118709..88a907a 100644 --- a/arch/arm/include/asm/arch-g12a/timing.h +++ b/arch/arm/include/asm/arch-g12a/timing.h @@ -54,57 +54,167 @@ /* etc... */ typedef struct bl2_reg { - unsigned int reg; - unsigned int value; - unsigned int mask; - unsigned short udelay; - unsigned char flag; - unsigned char rsv_0; + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; }__attribute__ ((packed)) bl2_reg_t; typedef struct ddr_reg { - unsigned int reg; - unsigned int value; - unsigned int mask; - unsigned short udelay; - unsigned char flag; - unsigned char rsv_0; + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; }__attribute__ ((packed)) ddr_reg_t; +typedef struct training_delay_set_ps{ + unsigned char ac_trace_delay[10]; + unsigned char ac_trace_delay_rev[2]; + unsigned char read_dqs_delay[16]; + unsigned char read_dq_bit_delay[72]; + unsigned short write_dqs_delay[16]; +// */ + unsigned short write_dq_bit_delay[72]; + unsigned short read_dqs_gate_delay[16]; + unsigned char soc_bit_vref[36]; + unsigned char dram_bit_vref[32]; + ///* + unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq + unsigned char dfi_mrl; + unsigned char dfi_hwtmrl; + unsigned char ARdPtrInitVal; + unsigned short csr_vrefinglobal; + unsigned short csr_dqsrcvcntrl[4]; + unsigned short csr_pptdqscntinvtrntg0[4]; + unsigned short csr_pptdqscntinvtrntg1[4]; + unsigned short csr_seq0bgpr[9]; + unsigned short csr_dllgainctl; + unsigned short csr_dlllockpara; +// unsigned short rever2; +}__attribute__ ((packed)) training_delay_set_ps_t; + +typedef struct ddr_mrs_reg { + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; +}__attribute__ ((packed)) ddr_mrs_reg_t; + +typedef struct ddr_timing{ + unsigned int identifier; + unsigned int cfg_ddr_mrd; + unsigned int cfg_ddr_rfcab; + unsigned int cfg_ddr_rfcpb; + unsigned int cfg_ddr_rpab; + unsigned int cfg_ddr_rppb; + unsigned int cfg_ddr_rtw; + unsigned int cfg_ddr_rl; + unsigned int cfg_ddr_wl; + unsigned int cfg_ddr_ras; + unsigned int cfg_ddr_rc; + unsigned int cfg_ddr_rcd; + unsigned int cfg_ddr_rrds; + unsigned int cfg_ddr_rrdl; + unsigned int cfg_ddr_faw; + unsigned int cfg_ddr_rtp; + unsigned int cfg_ddr_wr; + unsigned int cfg_ddr_wtrs; + unsigned int cfg_ddr_wtrl; + unsigned int cfg_ddr_ccds; + unsigned int cfg_ddr_ccdl; + unsigned int cfg_ddr_exsr; + unsigned int cfg_ddr_xs; + unsigned int cfg_ddr_xp; + unsigned int cfg_ddr_xpdll; + unsigned int cfg_ddr_zqcs; + unsigned int cfg_ddr_cksre; + unsigned int cfg_ddr_cksrx; + unsigned int cfg_ddr_cke; + unsigned int cfg_ddr_mod; + unsigned int cfg_ddr_dqs; + unsigned int cfg_ddr_rstl; + unsigned int cfg_ddr_zqlat; + unsigned int cfg_ddr_mrr; + unsigned int cfg_ddr_ckesr; + unsigned int cfg_ddr_dpd; + unsigned int cfg_ddr_ckeck; + unsigned int cfg_ddr_refi; + unsigned int cfg_ddr_sr; + unsigned int cfg_ddr_ccdmw; + unsigned int cfg_ddr_escke; + unsigned int cfg_ddr_refi_ddr3; + unsigned int cfg_ddr_dfictrldelay; + unsigned int cfg_ddr_dfiphywrdata; + unsigned int cfg_ddr_dfiphywrlat; + unsigned int cfg_ddr_dfiphyrddataen; + unsigned int cfg_ddr_dfiphyrdlat; + unsigned int cfg_ddr_dfictrlupdmin; + unsigned int cfg_ddr_dfictrlupdmax; + unsigned int cfg_ddr_dfimstrresp; + unsigned int cfg_ddr_dfirefmski; + unsigned int cfg_ddr_dfictrlupdi; + unsigned int cfg_ddr_dfidramclk; + unsigned int cfg_ddr_dfilpresp; + unsigned int cfg_ddr_dfiphymstr; + unsigned int cfg_ddr_rtodt; + unsigned int cfg_ddr_wlmrd; + unsigned int cfg_ddr_wlo; + unsigned int cfg_ddr_al; + unsigned int cfg_ddr_zqcl; + unsigned int cfg_ddr_zqcsi; + unsigned int cfg_ddr_zqreset; + unsigned int cfg_ddr_tdqsck_min; + unsigned int cfg_ddr_tdqsck_max; + //training_delay_set_ps_t cfg_ddr_training_delay_ps; + ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2]; + unsigned int dfi_odt1_config_ps[2]; + //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1; + #if 0 + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; + unsigned int cfg_ddr_reserve[5]; + #endif +}__attribute__ ((packed)) ddr_timing_t; + +typedef struct ddr_phy_common_extra_set{ + unsigned short csr_pllctrl3; + unsigned short csr_pptctlstatic[4]; + unsigned short csr_trainingincdecdtsmen[4]; + unsigned short csr_tsmbyte0[4]; + unsigned short csr_hwtcamode; + unsigned short csr_hwtlpcsena; + unsigned short csr_hwtlpcsenb; + unsigned short csr_acsmctrl13; + unsigned short csr_acsmctrl23; + unsigned char csr_soc_vref_dac1_dfe[36]; +}__attribute__ ((packed)) ddr_phy_common_extra_set_t; + typedef struct retraining_set{ - unsigned short csr_pllctrl3; - unsigned short csr_pptctlstatic[4]; - unsigned short csr_trainingincdecdtsmen[4]; - unsigned short csr_tsmbyte0[4]; - unsigned short csr_vrefinglobal; - //unsigned short csr_dfimrl[4]; - unsigned short csr_dqsrcvcntrl[4]; - unsigned short csr_pptdqscntinvtrntg0[4]; - unsigned short csr_pptdqscntinvtrntg1[4]; - unsigned short csr_seq0bgpr[9]; - //unsigned short csr_seq0bgpr2; - //unsigned short csr_seq0bgpr3; - //unsigned short csr_seq0bgpr4; - //unsigned short csr_seq0bgpr5; - //unsigned short csr_seq0bgpr6; - //unsigned short csr_seq0bgpr7; - //unsigned short csr_seq0bgpr8; - unsigned short csr_dllgainctl; - unsigned short csr_dlllockpara; - //unsigned short csr_hwtmrl; - unsigned short csr_hwtcamode; - unsigned short csr_hwtlpcsena; - unsigned short csr_hwtlpcsenb; - unsigned short csr_acsmctrl13; - unsigned short csr_acsmctrl23; - unsigned char csr_soc_vref_dac1_dfe[36]; - //unsigned short DqDqsRcvCntrl[8]; - //unsigned short rev_41; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps; }__attribute__ ((packed)) retraining_set_t; + typedef struct ddr_set{ unsigned int magic; unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test //unsigned int rsv_int0; + unsigned int ddr_func; unsigned char board_id; //board id reserve,,do not modify unsigned char version; @@ -140,12 +250,19 @@ typedef struct ddr_set{ /* rsv_char0. update for diagnose type define */ unsigned char diagnose; + unsigned short soc_data_drv_ohm_ps1; + unsigned short dram_data_drv_ohm_ps1; + unsigned short soc_data_odt_ohm_ps1; + unsigned short dram_data_odt_ohm_ps1; + unsigned short dram_data_wr_odt_ohm_ps1; + #if 0 /* imem/dmem define */ unsigned int imem_load_addr; //system reserve,do not modify unsigned int dmem_load_addr; //system reserve,do not modify unsigned short imem_load_size; + #endif //system reserve,do not modify unsigned short dmem_load_size; //system reserve,do not modify @@ -261,10 +378,6 @@ typedef struct ddr_set{ unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting; //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ unsigned char lpddr4_x8_mode; - //system reserve,do not modify ,take care ,please follow SI - unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; - //use for lpddr3 /lpddr4 ca pinmux remap - unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function //[1],slt test parameter ,use for force delay line offset //system reserve,do not modify @@ -273,116 +386,46 @@ typedef struct ddr_set{ unsigned char bitTimeControl_2d; //system reserve,do not modify /* align8 */ - + unsigned char char_rev1; + unsigned char char_rev2; unsigned int ddr_dmc_remap[5]; + unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify /* align8 */ - unsigned char ddr_lpddr34_ca_remap[4]; + unsigned char ddr_lpddr34_ca_remap[4]; ////use for lpddr3 /lpddr4 ca training data byte lane remap unsigned char ddr_lpddr34_dq_remap[32]; ////use for lpddr3 /lpddr4 ca pinmux remap - unsigned int dram_rtt_nom_wr_park[2]; - //system reserve,do not modify - unsigned int ddr_func; - //system reserve,do not modify - /* align8 */ - - //unsigned long rsv_long0[2]; - /* v1 end */ - //unsigned char read_dqs_adjust[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read - //unsigned char read_dq_bit_delay[72]; - //unsigned char write_dq_bit_delay[72]; + unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; + //use for lpddr3 /lpddr4 ca pinmux remap + unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; + unsigned char char_rev3; + unsigned char char_rev4; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps[2]; - unsigned char read_dqs_delay[16]; - unsigned char read_dq_bit_delay[72]; - unsigned short write_dqs_delay[16]; - unsigned short write_dq_bit_delay[72]; - unsigned short read_dqs_gate_delay[16]; - unsigned char soc_bit_vref[36]; - unsigned char dram_bit_vref[32]; - unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq - unsigned char dfi_mrl; - unsigned char dfi_hwtmrl; - unsigned char ARdPtrInitVal; - unsigned char retraining[16]; - retraining_set_t retraining_extra_set_t; //override read bit delay }__attribute__ ((packed)) ddr_set_t; -typedef struct ddr_timing{ - //Identifier - unsigned char identifier; - - //DTPR0 - unsigned char cfg_ddr_rtp; - unsigned char cfg_ddr_wtr; - unsigned char cfg_ddr_rp; - unsigned char cfg_ddr_rcd; - unsigned char cfg_ddr_ras; - unsigned char cfg_ddr_rrd; - unsigned char cfg_ddr_rc; - - //DTPR1 - unsigned char cfg_ddr_mrd; - unsigned char cfg_ddr_mod; - unsigned char cfg_ddr_faw; - unsigned char cfg_ddr_wlmrd; - unsigned char cfg_ddr_wlo; - - //DTPR2 - unsigned char cfg_ddr_xp; - - //DTPR1 - unsigned short cfg_ddr_rfc; - - //DTPR2 - unsigned short cfg_ddr_xs; - unsigned short cfg_ddr_dllk; - unsigned char cfg_ddr_cke; - unsigned char cfg_ddr_rtodt; - unsigned char cfg_ddr_rtw; - - unsigned char cfg_ddr_refi; - unsigned char cfg_ddr_refi_mddr3; - unsigned char cfg_ddr_cl; - unsigned char cfg_ddr_wr; - unsigned char cfg_ddr_cwl; - unsigned char cfg_ddr_al; - unsigned char cfg_ddr_dqs; - unsigned char cfg_ddr_cksre; - unsigned char cfg_ddr_cksrx; - unsigned char cfg_ddr_zqcs; - unsigned char cfg_ddr_xpdll; - unsigned short cfg_ddr_exsr; - unsigned short cfg_ddr_zqcl; - unsigned short cfg_ddr_zqcsi; - - unsigned char cfg_ddr_tccdl; - unsigned char cfg_ddr_tdqsck; - unsigned char cfg_ddr_tdqsckmax; - unsigned char rsv_char; - - /* reserved */ - unsigned int rsv_int; -}__attribute__ ((packed)) ddr_timing_t; - typedef struct pll_set{ - unsigned short cpu_clk; - unsigned short pxp; - unsigned int spi_ctrl; - unsigned short vddee; - unsigned short vcck; - unsigned char szPad[4]; - - unsigned long lCustomerID; - unsigned short debug_mode; - unsigned short rsv1; - unsigned int nCFGTAddr; + unsigned short cpu_clk; + unsigned short pxp; + unsigned int spi_ctrl; + unsigned short vddee; + unsigned short vcck; + unsigned char szPad[4]; + + unsigned long lCustomerID; + unsigned char debug_mode; + unsigned char log_chl; + unsigned char log_ctrl; + unsigned char ddr_timming_save_mode; + unsigned int nCFGTAddr; /* align 8Byte */ - unsigned int sys_pll_cntl[8]; - unsigned int ddr_pll_cntl[8]; - unsigned int fix_pll_cntl[8]; + unsigned int sys_pll_cntl[8]; + unsigned int ddr_pll_cntl[8]; + unsigned int fix_pll_cntl[8]; }__attribute__ ((packed)) pll_set_t; typedef struct dmem_cfg { diff --git a/arch/arm/include/asm/arch-g12b/acs.h b/arch/arm/include/asm/arch-g12b/acs.h index c65c647..bc35366 100644 --- a/arch/arm/include/asm/arch-g12b/acs.h +++ b/arch/arm/include/asm/arch-g12b/acs.h @@ -59,6 +59,9 @@ typedef struct acs_setting{ unsigned char rsv_set_version; unsigned short rsv_set_length; unsigned long rsv_set_addr; + char board_id[12]; + unsigned short ddr_struct_size[12]; + unsigned long ddr_struct_org_size; }__attribute__ ((packed)) acs_set_t; #endif diff --git a/arch/arm/include/asm/arch-g12b/ddr_define.h b/arch/arm/include/asm/arch-g12b/ddr_define.h index e4433f8..3ed19db 100644 --- a/arch/arm/include/asm/arch-g12b/ddr_define.h +++ b/arch/arm/include/asm/arch-g12b/ddr_define.h @@ -260,6 +260,7 @@ #endif #define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30) #define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29) +#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28) #define DDR_FUNC (DDR_FUNC_D2PLL | \ DDR_FUNC_LP | \ DDR_FUNC_ZQ_PD | \ diff --git a/arch/arm/include/asm/arch-g12b/timing.h b/arch/arm/include/asm/arch-g12b/timing.h index ccfd31f..88a907a 100644 --- a/arch/arm/include/asm/arch-g12b/timing.h +++ b/arch/arm/include/asm/arch-g12b/timing.h @@ -54,57 +54,167 @@ /* etc... */ typedef struct bl2_reg { - unsigned int reg; - unsigned int value; - unsigned int mask; - unsigned short udelay; - unsigned char flag; - unsigned char rsv_0; + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; }__attribute__ ((packed)) bl2_reg_t; typedef struct ddr_reg { - unsigned int reg; - unsigned int value; - unsigned int mask; - unsigned short udelay; - unsigned char flag; - unsigned char rsv_0; + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; }__attribute__ ((packed)) ddr_reg_t; +typedef struct training_delay_set_ps{ + unsigned char ac_trace_delay[10]; + unsigned char ac_trace_delay_rev[2]; + unsigned char read_dqs_delay[16]; + unsigned char read_dq_bit_delay[72]; + unsigned short write_dqs_delay[16]; +// */ + unsigned short write_dq_bit_delay[72]; + unsigned short read_dqs_gate_delay[16]; + unsigned char soc_bit_vref[36]; + unsigned char dram_bit_vref[32]; + ///* + unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq + unsigned char dfi_mrl; + unsigned char dfi_hwtmrl; + unsigned char ARdPtrInitVal; + unsigned short csr_vrefinglobal; + unsigned short csr_dqsrcvcntrl[4]; + unsigned short csr_pptdqscntinvtrntg0[4]; + unsigned short csr_pptdqscntinvtrntg1[4]; + unsigned short csr_seq0bgpr[9]; + unsigned short csr_dllgainctl; + unsigned short csr_dlllockpara; +// unsigned short rever2; +}__attribute__ ((packed)) training_delay_set_ps_t; + +typedef struct ddr_mrs_reg { + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; +}__attribute__ ((packed)) ddr_mrs_reg_t; + +typedef struct ddr_timing{ + unsigned int identifier; + unsigned int cfg_ddr_mrd; + unsigned int cfg_ddr_rfcab; + unsigned int cfg_ddr_rfcpb; + unsigned int cfg_ddr_rpab; + unsigned int cfg_ddr_rppb; + unsigned int cfg_ddr_rtw; + unsigned int cfg_ddr_rl; + unsigned int cfg_ddr_wl; + unsigned int cfg_ddr_ras; + unsigned int cfg_ddr_rc; + unsigned int cfg_ddr_rcd; + unsigned int cfg_ddr_rrds; + unsigned int cfg_ddr_rrdl; + unsigned int cfg_ddr_faw; + unsigned int cfg_ddr_rtp; + unsigned int cfg_ddr_wr; + unsigned int cfg_ddr_wtrs; + unsigned int cfg_ddr_wtrl; + unsigned int cfg_ddr_ccds; + unsigned int cfg_ddr_ccdl; + unsigned int cfg_ddr_exsr; + unsigned int cfg_ddr_xs; + unsigned int cfg_ddr_xp; + unsigned int cfg_ddr_xpdll; + unsigned int cfg_ddr_zqcs; + unsigned int cfg_ddr_cksre; + unsigned int cfg_ddr_cksrx; + unsigned int cfg_ddr_cke; + unsigned int cfg_ddr_mod; + unsigned int cfg_ddr_dqs; + unsigned int cfg_ddr_rstl; + unsigned int cfg_ddr_zqlat; + unsigned int cfg_ddr_mrr; + unsigned int cfg_ddr_ckesr; + unsigned int cfg_ddr_dpd; + unsigned int cfg_ddr_ckeck; + unsigned int cfg_ddr_refi; + unsigned int cfg_ddr_sr; + unsigned int cfg_ddr_ccdmw; + unsigned int cfg_ddr_escke; + unsigned int cfg_ddr_refi_ddr3; + unsigned int cfg_ddr_dfictrldelay; + unsigned int cfg_ddr_dfiphywrdata; + unsigned int cfg_ddr_dfiphywrlat; + unsigned int cfg_ddr_dfiphyrddataen; + unsigned int cfg_ddr_dfiphyrdlat; + unsigned int cfg_ddr_dfictrlupdmin; + unsigned int cfg_ddr_dfictrlupdmax; + unsigned int cfg_ddr_dfimstrresp; + unsigned int cfg_ddr_dfirefmski; + unsigned int cfg_ddr_dfictrlupdi; + unsigned int cfg_ddr_dfidramclk; + unsigned int cfg_ddr_dfilpresp; + unsigned int cfg_ddr_dfiphymstr; + unsigned int cfg_ddr_rtodt; + unsigned int cfg_ddr_wlmrd; + unsigned int cfg_ddr_wlo; + unsigned int cfg_ddr_al; + unsigned int cfg_ddr_zqcl; + unsigned int cfg_ddr_zqcsi; + unsigned int cfg_ddr_zqreset; + unsigned int cfg_ddr_tdqsck_min; + unsigned int cfg_ddr_tdqsck_max; + //training_delay_set_ps_t cfg_ddr_training_delay_ps; + ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2]; + unsigned int dfi_odt1_config_ps[2]; + //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1; + #if 0 + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; + unsigned int cfg_ddr_reserve[5]; + #endif +}__attribute__ ((packed)) ddr_timing_t; + +typedef struct ddr_phy_common_extra_set{ + unsigned short csr_pllctrl3; + unsigned short csr_pptctlstatic[4]; + unsigned short csr_trainingincdecdtsmen[4]; + unsigned short csr_tsmbyte0[4]; + unsigned short csr_hwtcamode; + unsigned short csr_hwtlpcsena; + unsigned short csr_hwtlpcsenb; + unsigned short csr_acsmctrl13; + unsigned short csr_acsmctrl23; + unsigned char csr_soc_vref_dac1_dfe[36]; +}__attribute__ ((packed)) ddr_phy_common_extra_set_t; + typedef struct retraining_set{ - unsigned short csr_pllctrl3; - unsigned short csr_pptctlstatic[4]; - unsigned short csr_trainingincdecdtsmen[4]; - unsigned short csr_tsmbyte0[4]; - unsigned short csr_vrefinglobal; - //unsigned short csr_dfimrl[4]; - unsigned short csr_dqsrcvcntrl[4]; - unsigned short csr_pptdqscntinvtrntg0[4]; - unsigned short csr_pptdqscntinvtrntg1[4]; - unsigned short csr_seq0bgpr[9]; - //unsigned short csr_seq0bgpr2; - //unsigned short csr_seq0bgpr3; - //unsigned short csr_seq0bgpr4; - //unsigned short csr_seq0bgpr5; - //unsigned short csr_seq0bgpr6; - //unsigned short csr_seq0bgpr7; - //unsigned short csr_seq0bgpr8; - unsigned short csr_dllgainctl; - unsigned short csr_dlllockpara; - //unsigned short csr_hwtmrl; - unsigned short csr_hwtcamode; - unsigned short csr_hwtlpcsena; - unsigned short csr_hwtlpcsenb; - unsigned short csr_acsmctrl13; - unsigned short csr_acsmctrl23; - unsigned char csr_soc_vref_dac1_dfe[36]; - //unsigned short DqDqsRcvCntrl[8]; - //unsigned short rev_41; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps; }__attribute__ ((packed)) retraining_set_t; + typedef struct ddr_set{ unsigned int magic; unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test //unsigned int rsv_int0; + unsigned int ddr_func; unsigned char board_id; //board id reserve,,do not modify unsigned char version; @@ -140,12 +250,19 @@ typedef struct ddr_set{ /* rsv_char0. update for diagnose type define */ unsigned char diagnose; + unsigned short soc_data_drv_ohm_ps1; + unsigned short dram_data_drv_ohm_ps1; + unsigned short soc_data_odt_ohm_ps1; + unsigned short dram_data_odt_ohm_ps1; + unsigned short dram_data_wr_odt_ohm_ps1; + #if 0 /* imem/dmem define */ unsigned int imem_load_addr; //system reserve,do not modify unsigned int dmem_load_addr; //system reserve,do not modify unsigned short imem_load_size; + #endif //system reserve,do not modify unsigned short dmem_load_size; //system reserve,do not modify @@ -261,10 +378,6 @@ typedef struct ddr_set{ unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting; //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ unsigned char lpddr4_x8_mode; - //system reserve,do not modify ,take care ,please follow SI - unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; - //use for lpddr3 /lpddr4 ca pinmux remap - unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function //[1],slt test parameter ,use for force delay line offset //system reserve,do not modify @@ -273,62 +386,46 @@ typedef struct ddr_set{ unsigned char bitTimeControl_2d; //system reserve,do not modify /* align8 */ - + unsigned char char_rev1; + unsigned char char_rev2; unsigned int ddr_dmc_remap[5]; + unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify /* align8 */ - unsigned char ddr_lpddr34_ca_remap[4]; + unsigned char ddr_lpddr34_ca_remap[4]; ////use for lpddr3 /lpddr4 ca training data byte lane remap unsigned char ddr_lpddr34_dq_remap[32]; ////use for lpddr3 /lpddr4 ca pinmux remap - unsigned int dram_rtt_nom_wr_park[2]; - //system reserve,do not modify - unsigned int ddr_func; - //system reserve,do not modify - /* align8 */ - - //unsigned long rsv_long0[2]; - /* v1 end */ - //unsigned char read_dqs_adjust[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read - //unsigned char read_dq_bit_delay[72]; - //unsigned char write_dq_bit_delay[72]; + unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; + //use for lpddr3 /lpddr4 ca pinmux remap + unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; + unsigned char char_rev3; + unsigned char char_rev4; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps[2]; - unsigned char read_dqs_delay[16]; - unsigned char read_dq_bit_delay[72]; - unsigned short write_dqs_delay[16]; -//*/ - unsigned short write_dq_bit_delay[72]; - unsigned short read_dqs_gate_delay[16]; - unsigned char soc_bit_vref[36]; - unsigned char dram_bit_vref[32]; -// /* - unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq - unsigned char dfi_mrl; - unsigned char dfi_hwtmrl; - unsigned char ARdPtrInitVal; - unsigned char retraining[16]; - retraining_set_t retraining_extra_set_t; //override read bit delay }__attribute__ ((packed)) ddr_set_t; typedef struct pll_set{ - unsigned short cpu_clk; - unsigned short pxp; - unsigned int spi_ctrl; - unsigned short vddee; - unsigned short vcck; - unsigned char szPad[4]; + unsigned short cpu_clk; + unsigned short pxp; + unsigned int spi_ctrl; + unsigned short vddee; + unsigned short vcck; + unsigned char szPad[4]; - unsigned long lCustomerID; - unsigned short debug_mode; - unsigned short rsv1; - unsigned short rsv2; - unsigned short rsv3; + unsigned long lCustomerID; + unsigned char debug_mode; + unsigned char log_chl; + unsigned char log_ctrl; + unsigned char ddr_timming_save_mode; + unsigned int nCFGTAddr; /* align 8Byte */ - unsigned int sys_pll_cntl[8]; - unsigned int ddr_pll_cntl[8]; - unsigned int fix_pll_cntl[8]; + unsigned int sys_pll_cntl[8]; + unsigned int ddr_pll_cntl[8]; + unsigned int fix_pll_cntl[8]; }__attribute__ ((packed)) pll_set_t; typedef struct dmem_cfg { @@ -340,4 +437,4 @@ typedef struct dmem_cfg { PMU_SMB_LPDDR4_2D_t lpddr4u_2d; } dmem_cfg_t; -#endif //__AML_TIMING_H_ +#endif //__AML_TIMING_H_
\ No newline at end of file diff --git a/arch/arm/include/asm/arch-tl1/acs.h b/arch/arm/include/asm/arch-tl1/acs.h index c65c647..bc35366 100644 --- a/arch/arm/include/asm/arch-tl1/acs.h +++ b/arch/arm/include/asm/arch-tl1/acs.h @@ -59,6 +59,9 @@ typedef struct acs_setting{ unsigned char rsv_set_version; unsigned short rsv_set_length; unsigned long rsv_set_addr; + char board_id[12]; + unsigned short ddr_struct_size[12]; + unsigned long ddr_struct_org_size; }__attribute__ ((packed)) acs_set_t; #endif diff --git a/arch/arm/include/asm/arch-tl1/ddr_define.h b/arch/arm/include/asm/arch-tl1/ddr_define.h index 2f1c7bb..a2ed223 100644 --- a/arch/arm/include/asm/arch-tl1/ddr_define.h +++ b/arch/arm/include/asm/arch-tl1/ddr_define.h @@ -248,6 +248,7 @@ #endif #define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30) #define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29) +#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28) #define DDR_FUNC (DDR_FUNC_D2PLL | \ DDR_FUNC_LP | \ DDR_FUNC_ZQ_PD | \ diff --git a/arch/arm/include/asm/arch-tl1/timing.h b/arch/arm/include/asm/arch-tl1/timing.h index 6bad442..8dc22f0 100644 --- a/arch/arm/include/asm/arch-tl1/timing.h +++ b/arch/arm/include/asm/arch-tl1/timing.h @@ -43,57 +43,167 @@ #define BL2_INIT_STAGE_9 9 typedef struct bl2_reg { - unsigned int reg; - unsigned int value; - unsigned int mask; - unsigned short udelay; - unsigned char flag; - unsigned char rsv_0; + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; }__attribute__ ((packed)) bl2_reg_t; typedef struct ddr_reg { - unsigned int reg; - unsigned int value; - unsigned int mask; - unsigned short udelay; - unsigned char flag; - unsigned char rsv_0; + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; }__attribute__ ((packed)) ddr_reg_t; +typedef struct training_delay_set_ps{ + unsigned char ac_trace_delay[10]; + unsigned char ac_trace_delay_rev[2]; + unsigned char read_dqs_delay[16]; + unsigned char read_dq_bit_delay[72]; + unsigned short write_dqs_delay[16]; +// */ + unsigned short write_dq_bit_delay[72]; + unsigned short read_dqs_gate_delay[16]; + unsigned char soc_bit_vref[36]; + unsigned char dram_bit_vref[32]; + ///* + unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq + unsigned char dfi_mrl; + unsigned char dfi_hwtmrl; + unsigned char ARdPtrInitVal; + unsigned short csr_vrefinglobal; + unsigned short csr_dqsrcvcntrl[4]; + unsigned short csr_pptdqscntinvtrntg0[4]; + unsigned short csr_pptdqscntinvtrntg1[4]; + unsigned short csr_seq0bgpr[9]; + unsigned short csr_dllgainctl; + unsigned short csr_dlllockpara; +// unsigned short rever2; +}__attribute__ ((packed)) training_delay_set_ps_t; + +typedef struct ddr_mrs_reg { + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; +}__attribute__ ((packed)) ddr_mrs_reg_t; + +typedef struct ddr_timing{ + unsigned int identifier; + unsigned int cfg_ddr_mrd; + unsigned int cfg_ddr_rfcab; + unsigned int cfg_ddr_rfcpb; + unsigned int cfg_ddr_rpab; + unsigned int cfg_ddr_rppb; + unsigned int cfg_ddr_rtw; + unsigned int cfg_ddr_rl; + unsigned int cfg_ddr_wl; + unsigned int cfg_ddr_ras; + unsigned int cfg_ddr_rc; + unsigned int cfg_ddr_rcd; + unsigned int cfg_ddr_rrds; + unsigned int cfg_ddr_rrdl; + unsigned int cfg_ddr_faw; + unsigned int cfg_ddr_rtp; + unsigned int cfg_ddr_wr; + unsigned int cfg_ddr_wtrs; + unsigned int cfg_ddr_wtrl; + unsigned int cfg_ddr_ccds; + unsigned int cfg_ddr_ccdl; + unsigned int cfg_ddr_exsr; + unsigned int cfg_ddr_xs; + unsigned int cfg_ddr_xp; + unsigned int cfg_ddr_xpdll; + unsigned int cfg_ddr_zqcs; + unsigned int cfg_ddr_cksre; + unsigned int cfg_ddr_cksrx; + unsigned int cfg_ddr_cke; + unsigned int cfg_ddr_mod; + unsigned int cfg_ddr_dqs; + unsigned int cfg_ddr_rstl; + unsigned int cfg_ddr_zqlat; + unsigned int cfg_ddr_mrr; + unsigned int cfg_ddr_ckesr; + unsigned int cfg_ddr_dpd; + unsigned int cfg_ddr_ckeck; + unsigned int cfg_ddr_refi; + unsigned int cfg_ddr_sr; + unsigned int cfg_ddr_ccdmw; + unsigned int cfg_ddr_escke; + unsigned int cfg_ddr_refi_ddr3; + unsigned int cfg_ddr_dfictrldelay; + unsigned int cfg_ddr_dfiphywrdata; + unsigned int cfg_ddr_dfiphywrlat; + unsigned int cfg_ddr_dfiphyrddataen; + unsigned int cfg_ddr_dfiphyrdlat; + unsigned int cfg_ddr_dfictrlupdmin; + unsigned int cfg_ddr_dfictrlupdmax; + unsigned int cfg_ddr_dfimstrresp; + unsigned int cfg_ddr_dfirefmski; + unsigned int cfg_ddr_dfictrlupdi; + unsigned int cfg_ddr_dfidramclk; + unsigned int cfg_ddr_dfilpresp; + unsigned int cfg_ddr_dfiphymstr; + unsigned int cfg_ddr_rtodt; + unsigned int cfg_ddr_wlmrd; + unsigned int cfg_ddr_wlo; + unsigned int cfg_ddr_al; + unsigned int cfg_ddr_zqcl; + unsigned int cfg_ddr_zqcsi; + unsigned int cfg_ddr_zqreset; + unsigned int cfg_ddr_tdqsck_min; + unsigned int cfg_ddr_tdqsck_max; + //training_delay_set_ps_t cfg_ddr_training_delay_ps; + ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2]; + unsigned int dfi_odt1_config_ps[2]; + //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1; + #if 0 + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; + unsigned int cfg_ddr_reserve[5]; + #endif +}__attribute__ ((packed)) ddr_timing_t; + +typedef struct ddr_phy_common_extra_set{ + unsigned short csr_pllctrl3; + unsigned short csr_pptctlstatic[4]; + unsigned short csr_trainingincdecdtsmen[4]; + unsigned short csr_tsmbyte0[4]; + unsigned short csr_hwtcamode; + unsigned short csr_hwtlpcsena; + unsigned short csr_hwtlpcsenb; + unsigned short csr_acsmctrl13; + unsigned short csr_acsmctrl23; + unsigned char csr_soc_vref_dac1_dfe[36]; +}__attribute__ ((packed)) ddr_phy_common_extra_set_t; + typedef struct retraining_set{ - unsigned short csr_pllctrl3; - unsigned short csr_pptctlstatic[4]; - unsigned short csr_trainingincdecdtsmen[4]; - unsigned short csr_tsmbyte0[4]; - unsigned short csr_vrefinglobal; - //unsigned short csr_dfimrl[4]; - unsigned short csr_dqsrcvcntrl[4]; - unsigned short csr_pptdqscntinvtrntg0[4]; - unsigned short csr_pptdqscntinvtrntg1[4]; - unsigned short csr_seq0bgpr[9]; - //unsigned short csr_seq0bgpr2; - //unsigned short csr_seq0bgpr3; - //unsigned short csr_seq0bgpr4; - //unsigned short csr_seq0bgpr5; - //unsigned short csr_seq0bgpr6; - //unsigned short csr_seq0bgpr7; - //unsigned short csr_seq0bgpr8; - unsigned short csr_dllgainctl; - unsigned short csr_dlllockpara; - //unsigned short csr_hwtmrl; - unsigned short csr_hwtcamode; - unsigned short csr_hwtlpcsena; - unsigned short csr_hwtlpcsenb; - unsigned short csr_acsmctrl13; - unsigned short csr_acsmctrl23; - unsigned char csr_soc_vref_dac1_dfe[36]; - //unsigned short DqDqsRcvCntrl[8]; - //unsigned short rev_41; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps; }__attribute__ ((packed)) retraining_set_t; + typedef struct ddr_set{ unsigned int magic; unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test //unsigned int rsv_int0; + unsigned int ddr_func; unsigned char board_id; //board id reserve,,do not modify unsigned char version; @@ -129,12 +239,19 @@ typedef struct ddr_set{ /* rsv_char0. update for diagnose type define */ unsigned char diagnose; + unsigned short soc_data_drv_ohm_ps1; + unsigned short dram_data_drv_ohm_ps1; + unsigned short soc_data_odt_ohm_ps1; + unsigned short dram_data_odt_ohm_ps1; + unsigned short dram_data_wr_odt_ohm_ps1; + #if 0 /* imem/dmem define */ unsigned int imem_load_addr; //system reserve,do not modify unsigned int dmem_load_addr; //system reserve,do not modify unsigned short imem_load_size; + #endif //system reserve,do not modify unsigned short dmem_load_size; //system reserve,do not modify @@ -244,15 +361,12 @@ typedef struct ddr_set{ //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI unsigned short max_core_timmming_frequency; //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register + /* align8 */ unsigned char ac_trace_delay[10]; unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting; //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ unsigned char lpddr4_x8_mode; - //system reserve,do not modify ,take care ,please follow SI - unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; - //use for lpddr3 /lpddr4 ca pinmux remap - unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function //[1],slt test parameter ,use for force delay line offset //system reserve,do not modify @@ -261,119 +375,46 @@ typedef struct ddr_set{ unsigned char bitTimeControl_2d; //system reserve,do not modify /* align8 */ - + unsigned char char_rev1; + unsigned char char_rev2; unsigned int ddr_dmc_remap[5]; + unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify /* align8 */ - unsigned char ddr_lpddr34_ca_remap[4]; + unsigned char ddr_lpddr34_ca_remap[4]; ////use for lpddr3 /lpddr4 ca training data byte lane remap unsigned char ddr_lpddr34_dq_remap[32]; ////use for lpddr3 /lpddr4 ca pinmux remap - unsigned int dram_rtt_nom_wr_park[2]; - //system reserve,do not modify - unsigned int ddr_func; - //system reserve,do not modify - /* align8 */ - - //unsigned long rsv_long0[2]; - /* v1 end */ - //unsigned char read_dqs_adjust[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read - //unsigned char read_dq_bit_delay[72]; - //unsigned char write_dq_bit_delay[72]; + unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; + //use for lpddr3 /lpddr4 ca pinmux remap + unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; + unsigned char char_rev3; + unsigned char char_rev4; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps[2]; -///* - unsigned char read_dqs_delay[16]; - unsigned char read_dq_bit_delay[72]; - unsigned short write_dqs_delay[16]; -//*/ - unsigned short write_dq_bit_delay[72]; - unsigned short read_dqs_gate_delay[16]; - unsigned char soc_bit_vref[36]; - unsigned char dram_bit_vref[32]; -// /* - unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq - unsigned char dfi_mrl; - unsigned char dfi_hwtmrl; - unsigned char ARdPtrInitVal; - unsigned char retraining[16]; - retraining_set_t retraining_extra_set_t; //override read bit delay }__attribute__ ((packed)) ddr_set_t; -typedef struct ddr_timing{ - //Identifier - unsigned char identifier; - - //DTPR0 - unsigned char cfg_ddr_rtp; - unsigned char cfg_ddr_wtr; - unsigned char cfg_ddr_rp; - unsigned char cfg_ddr_rcd; - unsigned char cfg_ddr_ras; - unsigned char cfg_ddr_rrd; - unsigned char cfg_ddr_rc; - - //DTPR1 - unsigned char cfg_ddr_mrd; - unsigned char cfg_ddr_mod; - unsigned char cfg_ddr_faw; - unsigned char cfg_ddr_wlmrd; - unsigned char cfg_ddr_wlo; - - //DTPR2 - unsigned char cfg_ddr_xp; - - //DTPR1 - unsigned short cfg_ddr_rfc; - - //DTPR2 - unsigned short cfg_ddr_xs; - unsigned short cfg_ddr_dllk; - unsigned char cfg_ddr_cke; - unsigned char cfg_ddr_rtodt; - unsigned char cfg_ddr_rtw; - - unsigned char cfg_ddr_refi; - unsigned char cfg_ddr_refi_mddr3; - unsigned char cfg_ddr_cl; - unsigned char cfg_ddr_wr; - unsigned char cfg_ddr_cwl; - unsigned char cfg_ddr_al; - unsigned char cfg_ddr_dqs; - unsigned char cfg_ddr_cksre; - unsigned char cfg_ddr_cksrx; - unsigned char cfg_ddr_zqcs; - unsigned char cfg_ddr_xpdll; - unsigned short cfg_ddr_exsr; - unsigned short cfg_ddr_zqcl; - unsigned short cfg_ddr_zqcsi; - - unsigned char cfg_ddr_tccdl; - unsigned char cfg_ddr_tdqsck; - unsigned char cfg_ddr_tdqsckmax; - unsigned char rsv_char; - - /* reserved */ - unsigned int rsv_int; -}__attribute__ ((packed)) ddr_timing_t; - typedef struct pll_set{ - unsigned short cpu_clk; - unsigned short pxp; - unsigned int spi_ctrl; - unsigned short vddee; - unsigned short vcck; - unsigned char szPad[4]; + unsigned short cpu_clk; + unsigned short pxp; + unsigned int spi_ctrl; + unsigned short vddee; + unsigned short vcck; + unsigned char szPad[4]; - unsigned long lCustomerID; - unsigned short debug_mode; - unsigned short rsv1; - unsigned int nCFGTAddr; + unsigned long lCustomerID; + unsigned char debug_mode; + unsigned char log_chl; + unsigned char log_ctrl; + unsigned char ddr_timming_save_mode; + unsigned int nCFGTAddr; /* align 8Byte */ - unsigned int sys_pll_cntl[8]; - unsigned int ddr_pll_cntl[8]; - unsigned int fix_pll_cntl[8]; + unsigned int sys_pll_cntl[8]; + unsigned int ddr_pll_cntl[8]; + unsigned int fix_pll_cntl[8]; }__attribute__ ((packed)) pll_set_t; typedef struct dmem_cfg { diff --git a/arch/arm/include/asm/arch-tm2/acs.h b/arch/arm/include/asm/arch-tm2/acs.h index c65c647..bc35366 100644 --- a/arch/arm/include/asm/arch-tm2/acs.h +++ b/arch/arm/include/asm/arch-tm2/acs.h @@ -59,6 +59,9 @@ typedef struct acs_setting{ unsigned char rsv_set_version; unsigned short rsv_set_length; unsigned long rsv_set_addr; + char board_id[12]; + unsigned short ddr_struct_size[12]; + unsigned long ddr_struct_org_size; }__attribute__ ((packed)) acs_set_t; #endif diff --git a/arch/arm/include/asm/arch-tm2/ddr_define.h b/arch/arm/include/asm/arch-tm2/ddr_define.h index 2f1c7bb..a2ed223 100644 --- a/arch/arm/include/asm/arch-tm2/ddr_define.h +++ b/arch/arm/include/asm/arch-tm2/ddr_define.h @@ -248,6 +248,7 @@ #endif #define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30) #define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29) +#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28) #define DDR_FUNC (DDR_FUNC_D2PLL | \ DDR_FUNC_LP | \ DDR_FUNC_ZQ_PD | \ diff --git a/arch/arm/include/asm/arch-tm2/timing.h b/arch/arm/include/asm/arch-tm2/timing.h index 6bad442..8dc22f0 100644 --- a/arch/arm/include/asm/arch-tm2/timing.h +++ b/arch/arm/include/asm/arch-tm2/timing.h @@ -43,57 +43,167 @@ #define BL2_INIT_STAGE_9 9 typedef struct bl2_reg { - unsigned int reg; - unsigned int value; - unsigned int mask; - unsigned short udelay; - unsigned char flag; - unsigned char rsv_0; + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; }__attribute__ ((packed)) bl2_reg_t; typedef struct ddr_reg { - unsigned int reg; - unsigned int value; - unsigned int mask; - unsigned short udelay; - unsigned char flag; - unsigned char rsv_0; + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; }__attribute__ ((packed)) ddr_reg_t; +typedef struct training_delay_set_ps{ + unsigned char ac_trace_delay[10]; + unsigned char ac_trace_delay_rev[2]; + unsigned char read_dqs_delay[16]; + unsigned char read_dq_bit_delay[72]; + unsigned short write_dqs_delay[16]; +// */ + unsigned short write_dq_bit_delay[72]; + unsigned short read_dqs_gate_delay[16]; + unsigned char soc_bit_vref[36]; + unsigned char dram_bit_vref[32]; + ///* + unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq + unsigned char dfi_mrl; + unsigned char dfi_hwtmrl; + unsigned char ARdPtrInitVal; + unsigned short csr_vrefinglobal; + unsigned short csr_dqsrcvcntrl[4]; + unsigned short csr_pptdqscntinvtrntg0[4]; + unsigned short csr_pptdqscntinvtrntg1[4]; + unsigned short csr_seq0bgpr[9]; + unsigned short csr_dllgainctl; + unsigned short csr_dlllockpara; +// unsigned short rever2; +}__attribute__ ((packed)) training_delay_set_ps_t; + +typedef struct ddr_mrs_reg { + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; +}__attribute__ ((packed)) ddr_mrs_reg_t; + +typedef struct ddr_timing{ + unsigned int identifier; + unsigned int cfg_ddr_mrd; + unsigned int cfg_ddr_rfcab; + unsigned int cfg_ddr_rfcpb; + unsigned int cfg_ddr_rpab; + unsigned int cfg_ddr_rppb; + unsigned int cfg_ddr_rtw; + unsigned int cfg_ddr_rl; + unsigned int cfg_ddr_wl; + unsigned int cfg_ddr_ras; + unsigned int cfg_ddr_rc; + unsigned int cfg_ddr_rcd; + unsigned int cfg_ddr_rrds; + unsigned int cfg_ddr_rrdl; + unsigned int cfg_ddr_faw; + unsigned int cfg_ddr_rtp; + unsigned int cfg_ddr_wr; + unsigned int cfg_ddr_wtrs; + unsigned int cfg_ddr_wtrl; + unsigned int cfg_ddr_ccds; + unsigned int cfg_ddr_ccdl; + unsigned int cfg_ddr_exsr; + unsigned int cfg_ddr_xs; + unsigned int cfg_ddr_xp; + unsigned int cfg_ddr_xpdll; + unsigned int cfg_ddr_zqcs; + unsigned int cfg_ddr_cksre; + unsigned int cfg_ddr_cksrx; + unsigned int cfg_ddr_cke; + unsigned int cfg_ddr_mod; + unsigned int cfg_ddr_dqs; + unsigned int cfg_ddr_rstl; + unsigned int cfg_ddr_zqlat; + unsigned int cfg_ddr_mrr; + unsigned int cfg_ddr_ckesr; + unsigned int cfg_ddr_dpd; + unsigned int cfg_ddr_ckeck; + unsigned int cfg_ddr_refi; + unsigned int cfg_ddr_sr; + unsigned int cfg_ddr_ccdmw; + unsigned int cfg_ddr_escke; + unsigned int cfg_ddr_refi_ddr3; + unsigned int cfg_ddr_dfictrldelay; + unsigned int cfg_ddr_dfiphywrdata; + unsigned int cfg_ddr_dfiphywrlat; + unsigned int cfg_ddr_dfiphyrddataen; + unsigned int cfg_ddr_dfiphyrdlat; + unsigned int cfg_ddr_dfictrlupdmin; + unsigned int cfg_ddr_dfictrlupdmax; + unsigned int cfg_ddr_dfimstrresp; + unsigned int cfg_ddr_dfirefmski; + unsigned int cfg_ddr_dfictrlupdi; + unsigned int cfg_ddr_dfidramclk; + unsigned int cfg_ddr_dfilpresp; + unsigned int cfg_ddr_dfiphymstr; + unsigned int cfg_ddr_rtodt; + unsigned int cfg_ddr_wlmrd; + unsigned int cfg_ddr_wlo; + unsigned int cfg_ddr_al; + unsigned int cfg_ddr_zqcl; + unsigned int cfg_ddr_zqcsi; + unsigned int cfg_ddr_zqreset; + unsigned int cfg_ddr_tdqsck_min; + unsigned int cfg_ddr_tdqsck_max; + //training_delay_set_ps_t cfg_ddr_training_delay_ps; + ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2]; + unsigned int dfi_odt1_config_ps[2]; + //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1; + #if 0 + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; + unsigned int cfg_ddr_reserve[5]; + #endif +}__attribute__ ((packed)) ddr_timing_t; + +typedef struct ddr_phy_common_extra_set{ + unsigned short csr_pllctrl3; + unsigned short csr_pptctlstatic[4]; + unsigned short csr_trainingincdecdtsmen[4]; + unsigned short csr_tsmbyte0[4]; + unsigned short csr_hwtcamode; + unsigned short csr_hwtlpcsena; + unsigned short csr_hwtlpcsenb; + unsigned short csr_acsmctrl13; + unsigned short csr_acsmctrl23; + unsigned char csr_soc_vref_dac1_dfe[36]; +}__attribute__ ((packed)) ddr_phy_common_extra_set_t; + typedef struct retraining_set{ - unsigned short csr_pllctrl3; - unsigned short csr_pptctlstatic[4]; - unsigned short csr_trainingincdecdtsmen[4]; - unsigned short csr_tsmbyte0[4]; - unsigned short csr_vrefinglobal; - //unsigned short csr_dfimrl[4]; - unsigned short csr_dqsrcvcntrl[4]; - unsigned short csr_pptdqscntinvtrntg0[4]; - unsigned short csr_pptdqscntinvtrntg1[4]; - unsigned short csr_seq0bgpr[9]; - //unsigned short csr_seq0bgpr2; - //unsigned short csr_seq0bgpr3; - //unsigned short csr_seq0bgpr4; - //unsigned short csr_seq0bgpr5; - //unsigned short csr_seq0bgpr6; - //unsigned short csr_seq0bgpr7; - //unsigned short csr_seq0bgpr8; - unsigned short csr_dllgainctl; - unsigned short csr_dlllockpara; - //unsigned short csr_hwtmrl; - unsigned short csr_hwtcamode; - unsigned short csr_hwtlpcsena; - unsigned short csr_hwtlpcsenb; - unsigned short csr_acsmctrl13; - unsigned short csr_acsmctrl23; - unsigned char csr_soc_vref_dac1_dfe[36]; - //unsigned short DqDqsRcvCntrl[8]; - //unsigned short rev_41; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps; }__attribute__ ((packed)) retraining_set_t; + typedef struct ddr_set{ unsigned int magic; unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test //unsigned int rsv_int0; + unsigned int ddr_func; unsigned char board_id; //board id reserve,,do not modify unsigned char version; @@ -129,12 +239,19 @@ typedef struct ddr_set{ /* rsv_char0. update for diagnose type define */ unsigned char diagnose; + unsigned short soc_data_drv_ohm_ps1; + unsigned short dram_data_drv_ohm_ps1; + unsigned short soc_data_odt_ohm_ps1; + unsigned short dram_data_odt_ohm_ps1; + unsigned short dram_data_wr_odt_ohm_ps1; + #if 0 /* imem/dmem define */ unsigned int imem_load_addr; //system reserve,do not modify unsigned int dmem_load_addr; //system reserve,do not modify unsigned short imem_load_size; + #endif //system reserve,do not modify unsigned short dmem_load_size; //system reserve,do not modify @@ -244,15 +361,12 @@ typedef struct ddr_set{ //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI unsigned short max_core_timmming_frequency; //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register + /* align8 */ unsigned char ac_trace_delay[10]; unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting; //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ unsigned char lpddr4_x8_mode; - //system reserve,do not modify ,take care ,please follow SI - unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; - //use for lpddr3 /lpddr4 ca pinmux remap - unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function //[1],slt test parameter ,use for force delay line offset //system reserve,do not modify @@ -261,119 +375,46 @@ typedef struct ddr_set{ unsigned char bitTimeControl_2d; //system reserve,do not modify /* align8 */ - + unsigned char char_rev1; + unsigned char char_rev2; unsigned int ddr_dmc_remap[5]; + unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify /* align8 */ - unsigned char ddr_lpddr34_ca_remap[4]; + unsigned char ddr_lpddr34_ca_remap[4]; ////use for lpddr3 /lpddr4 ca training data byte lane remap unsigned char ddr_lpddr34_dq_remap[32]; ////use for lpddr3 /lpddr4 ca pinmux remap - unsigned int dram_rtt_nom_wr_park[2]; - //system reserve,do not modify - unsigned int ddr_func; - //system reserve,do not modify - /* align8 */ - - //unsigned long rsv_long0[2]; - /* v1 end */ - //unsigned char read_dqs_adjust[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read - //unsigned char read_dq_bit_delay[72]; - //unsigned char write_dq_bit_delay[72]; + unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; + //use for lpddr3 /lpddr4 ca pinmux remap + unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; + unsigned char char_rev3; + unsigned char char_rev4; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps[2]; -///* - unsigned char read_dqs_delay[16]; - unsigned char read_dq_bit_delay[72]; - unsigned short write_dqs_delay[16]; -//*/ - unsigned short write_dq_bit_delay[72]; - unsigned short read_dqs_gate_delay[16]; - unsigned char soc_bit_vref[36]; - unsigned char dram_bit_vref[32]; -// /* - unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq - unsigned char dfi_mrl; - unsigned char dfi_hwtmrl; - unsigned char ARdPtrInitVal; - unsigned char retraining[16]; - retraining_set_t retraining_extra_set_t; //override read bit delay }__attribute__ ((packed)) ddr_set_t; -typedef struct ddr_timing{ - //Identifier - unsigned char identifier; - - //DTPR0 - unsigned char cfg_ddr_rtp; - unsigned char cfg_ddr_wtr; - unsigned char cfg_ddr_rp; - unsigned char cfg_ddr_rcd; - unsigned char cfg_ddr_ras; - unsigned char cfg_ddr_rrd; - unsigned char cfg_ddr_rc; - - //DTPR1 - unsigned char cfg_ddr_mrd; - unsigned char cfg_ddr_mod; - unsigned char cfg_ddr_faw; - unsigned char cfg_ddr_wlmrd; - unsigned char cfg_ddr_wlo; - - //DTPR2 - unsigned char cfg_ddr_xp; - - //DTPR1 - unsigned short cfg_ddr_rfc; - - //DTPR2 - unsigned short cfg_ddr_xs; - unsigned short cfg_ddr_dllk; - unsigned char cfg_ddr_cke; - unsigned char cfg_ddr_rtodt; - unsigned char cfg_ddr_rtw; - - unsigned char cfg_ddr_refi; - unsigned char cfg_ddr_refi_mddr3; - unsigned char cfg_ddr_cl; - unsigned char cfg_ddr_wr; - unsigned char cfg_ddr_cwl; - unsigned char cfg_ddr_al; - unsigned char cfg_ddr_dqs; - unsigned char cfg_ddr_cksre; - unsigned char cfg_ddr_cksrx; - unsigned char cfg_ddr_zqcs; - unsigned char cfg_ddr_xpdll; - unsigned short cfg_ddr_exsr; - unsigned short cfg_ddr_zqcl; - unsigned short cfg_ddr_zqcsi; - - unsigned char cfg_ddr_tccdl; - unsigned char cfg_ddr_tdqsck; - unsigned char cfg_ddr_tdqsckmax; - unsigned char rsv_char; - - /* reserved */ - unsigned int rsv_int; -}__attribute__ ((packed)) ddr_timing_t; - typedef struct pll_set{ - unsigned short cpu_clk; - unsigned short pxp; - unsigned int spi_ctrl; - unsigned short vddee; - unsigned short vcck; - unsigned char szPad[4]; + unsigned short cpu_clk; + unsigned short pxp; + unsigned int spi_ctrl; + unsigned short vddee; + unsigned short vcck; + unsigned char szPad[4]; - unsigned long lCustomerID; - unsigned short debug_mode; - unsigned short rsv1; - unsigned int nCFGTAddr; + unsigned long lCustomerID; + unsigned char debug_mode; + unsigned char log_chl; + unsigned char log_ctrl; + unsigned char ddr_timming_save_mode; + unsigned int nCFGTAddr; /* align 8Byte */ - unsigned int sys_pll_cntl[8]; - unsigned int ddr_pll_cntl[8]; - unsigned int fix_pll_cntl[8]; + unsigned int sys_pll_cntl[8]; + unsigned int ddr_pll_cntl[8]; + unsigned int fix_pll_cntl[8]; }__attribute__ ((packed)) pll_set_t; typedef struct dmem_cfg { diff --git a/board/amlogic/g12a_deadpool_v1/firmware/timing.c b/board/amlogic/g12a_deadpool_v1/firmware/timing.c index 1f1f2e9..0f34dc0 100644 --- a/board/amlogic/g12a_deadpool_v1/firmware/timing.c +++ b/board/amlogic/g12a_deadpool_v1/firmware/timing.c @@ -140,8 +140,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, diff --git a/board/amlogic/g12a_skt_v1/firmware/timing.c b/board/amlogic/g12a_skt_v1/firmware/timing.c index 43b83c1..2ec413e 100644 --- a/board/amlogic/g12a_skt_v1/firmware/timing.c +++ b/board/amlogic/g12a_skt_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -237,8 +237,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -320,8 +320,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -488,8 +488,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -561,8 +561,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {600, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/g12a_u200_v1/firmware/timing.c b/board/amlogic/g12a_u200_v1/firmware/timing.c index 2fa76b4..fb1774e 100644 --- a/board/amlogic/g12a_u200_v1/firmware/timing.c +++ b/board/amlogic/g12a_u200_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -139,8 +139,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -223,8 +223,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -298,8 +298,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -371,8 +371,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {600, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/g12a_u202_v1/firmware/timing.c b/board/amlogic/g12a_u202_v1/firmware/timing.c index 4d0feb2..dde3d89 100644 --- a/board/amlogic/g12a_u202_v1/firmware/timing.c +++ b/board/amlogic/g12a_u202_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -139,8 +139,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -223,8 +223,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -298,8 +298,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -371,8 +371,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {600, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/g12a_u211_v1/firmware/timing.c b/board/amlogic/g12a_u211_v1/firmware/timing.c index f22a21d..f9a7fdc 100644 --- a/board/amlogic/g12a_u211_v1/firmware/timing.c +++ b/board/amlogic/g12a_u211_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -139,8 +139,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -223,8 +223,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -297,8 +297,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -370,8 +370,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {600, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/g12a_u212_v1/firmware/timing.c b/board/amlogic/g12a_u212_v1/firmware/timing.c index 62ee74f..f5770a3 100644 --- a/board/amlogic/g12a_u212_v1/firmware/timing.c +++ b/board/amlogic/g12a_u212_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -138,8 +138,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -222,8 +222,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -295,8 +295,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -367,8 +367,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {600, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/g12a_u220_v1/firmware/timing.c b/board/amlogic/g12a_u220_v1/firmware/timing.c index 123da62..cdcfeba 100644 --- a/board/amlogic/g12a_u220_v1/firmware/timing.c +++ b/board/amlogic/g12a_u220_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -139,8 +139,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -223,8 +223,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1200, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -311,8 +311,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1200, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -385,8 +385,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -458,8 +458,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {600, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/g12a_u223_v1/firmware/timing.c b/board/amlogic/g12a_u223_v1/firmware/timing.c index 454b318..5566207 100644 --- a/board/amlogic/g12a_u223_v1/firmware/timing.c +++ b/board/amlogic/g12a_u223_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -139,8 +139,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {792, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -223,8 +223,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {792, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -297,8 +297,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {792, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -370,8 +370,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {792, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/g12b_skt_v1/firmware/timing.c b/board/amlogic/g12b_skt_v1/firmware/timing.c index 44b7707..6ff9f87 100644 --- a/board/amlogic/g12b_skt_v1/firmware/timing.c +++ b/board/amlogic/g12b_skt_v1/firmware/timing.c @@ -70,8 +70,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -145,8 +145,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -215,8 +215,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -299,8 +299,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -374,8 +374,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/g12b_w200_v1/firmware/timing.c b/board/amlogic/g12b_w200_v1/firmware/timing.c index c8daaa7..19b17bf 100644 --- a/board/amlogic/g12b_w200_v1/firmware/timing.c +++ b/board/amlogic/g12b_w200_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -140,8 +140,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -225,8 +225,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/g12b_w400_v1/firmware/timing.c b/board/amlogic/g12b_w400_v1/firmware/timing.c index 019dc32..685db26 100644 --- a/board/amlogic/g12b_w400_v1/firmware/timing.c +++ b/board/amlogic/g12b_w400_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -140,8 +140,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -225,8 +225,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/g12b_w411_v1/firmware/timing.c b/board/amlogic/g12b_w411_v1/firmware/timing.c index 77e6ea6..815326b 100644 --- a/board/amlogic/g12b_w411_v1/firmware/timing.c +++ b/board/amlogic/g12b_w411_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -139,8 +139,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -223,8 +223,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -298,8 +298,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/sm1_ac214_v1/firmware/timing.c b/board/amlogic/sm1_ac214_v1/firmware/timing.c index f22a21d..f9a7fdc 100644 --- a/board/amlogic/sm1_ac214_v1/firmware/timing.c +++ b/board/amlogic/sm1_ac214_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -139,8 +139,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -223,8 +223,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -297,8 +297,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -370,8 +370,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {600, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/board/amlogic/sm1_ac223_v1/firmware/timing.c b/board/amlogic/sm1_ac223_v1/firmware/timing.c index 454b318..5566207 100644 --- a/board/amlogic/sm1_ac223_v1/firmware/timing.c +++ b/board/amlogic/sm1_ac223_v1/firmware/timing.c @@ -69,8 +69,8 @@ ddr_set_t __ddr_setting[] = { .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -139,8 +139,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {792, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -223,8 +223,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {792, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -297,8 +297,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {792, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -370,8 +370,8 @@ ddr_set_t __ddr_setting[] = { .DRAMFreq = {792, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, diff --git a/common/cmd_ddr_test_g12.c b/common/cmd_ddr_test_g12.c index b0b8075..77f6b0e 100644 --- a/common/cmd_ddr_test_g12.c +++ b/common/cmd_ddr_test_g12.c @@ -101,7 +101,7 @@ int ddr_get_chip_id(void) //return CHIP_ID_MASK; } -char CMD_VER[] = "Ver_13"; +char CMD_VER[] = "Ver_14"; ddr_base_address_table_t __ddr_base_address_table[] = { //g12a { @@ -322,6 +322,44 @@ static uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_ *(volatile uint32_t *)(( unsigned long )(addr_t))=write_value; return write_value; } +typedef struct training_delay_set_ps{ + unsigned char ac_trace_delay[10]; + unsigned char ac_trace_delay_rev[2]; + unsigned char read_dqs_delay[16]; + unsigned char read_dq_bit_delay[72]; + unsigned short write_dqs_delay[16]; +// */ + unsigned short write_dq_bit_delay[72]; + unsigned short read_dqs_gate_delay[16]; + unsigned char soc_bit_vref[36]; + unsigned char dram_bit_vref[32]; + ///* + unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq + unsigned char dfi_mrl; + unsigned char dfi_hwtmrl; + unsigned char ARdPtrInitVal; + unsigned short csr_vrefinglobal; + unsigned short csr_dqsrcvcntrl[4]; + unsigned short csr_pptdqscntinvtrntg0[4]; + unsigned short csr_pptdqscntinvtrntg1[4]; + unsigned short csr_seq0bgpr[9]; + unsigned short csr_dllgainctl; + unsigned short csr_dlllockpara; +// unsigned short rever2; +}__attribute__ ((packed)) training_delay_set_ps_t; +typedef struct ddr_phy_common_extra_set{ + unsigned short csr_pllctrl3; + unsigned short csr_pptctlstatic[4]; + unsigned short csr_trainingincdecdtsmen[4]; + unsigned short csr_tsmbyte0[4]; + unsigned short csr_hwtcamode; + unsigned short csr_hwtlpcsena; + unsigned short csr_hwtlpcsenb; + unsigned short csr_acsmctrl13; + unsigned short csr_acsmctrl23; + unsigned char csr_soc_vref_dac1_dfe[36]; +}__attribute__ ((packed)) ddr_phy_common_extra_set_t; + typedef struct retraining_set{ unsigned short csr_pllctrl3; unsigned short csr_pptctlstatic[4]; @@ -355,6 +393,7 @@ typedef struct ddr_set{ unsigned int magic; unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test // unsigned int rsv_int0; + unsigned int ddr_func; unsigned char board_id; //board id reserve,,do not modify unsigned char version; @@ -390,12 +429,19 @@ typedef struct ddr_set{ /* rsv_char0. update for diagnose type define */ unsigned char diagnose; + unsigned short soc_data_drv_ohm_ps1; + unsigned short dram_data_drv_ohm_ps1; + unsigned short soc_data_odt_ohm_ps1; + unsigned short dram_data_odt_ohm_ps1; + unsigned short dram_data_wr_odt_ohm_ps1; + #if 0 /* imem/dmem define */ unsigned int imem_load_addr; //system reserve,do not modify unsigned int dmem_load_addr; //system reserve,do not modify unsigned short imem_load_size; + #endif //system reserve,do not modify unsigned short dmem_load_size; //system reserve,do not modify @@ -510,10 +556,6 @@ typedef struct ddr_set{ unsigned char ac_trace_delay[10]; unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting; unsigned char lpddr4_x8_mode; - //system reserve,do not modify ,take care ,please follow SI - unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; - //use for lpddr3 /lpddr4 ca pinmux remap - unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function //[1],slt test parameter ,use for force delay line offset //system reserve,do not modify @@ -522,38 +564,24 @@ typedef struct ddr_set{ unsigned char bitTimeControl_2d; //system reserve,do not modify /* align8 */ - + unsigned char char_rev1; + unsigned char char_rev2; unsigned int ddr_dmc_remap[5]; + unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify /* align8 */ unsigned char ddr_lpddr34_ca_remap[4]; ////use for lpddr3 /lpddr4 ca training data byte lane remap unsigned char ddr_lpddr34_dq_remap[32]; ////use for lpddr3 /lpddr4 ca pinmux remap - unsigned int dram_rtt_nom_wr_park[2]; - //system reserve,do not modify - unsigned int ddr_func; - //system reserve,do not modify - /* align8 */ + unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; + //use for lpddr3 /lpddr4 ca pinmux remap + unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; + unsigned char char_rev3; + unsigned char char_rev4; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps[2]; - //unsigned long rsv_long0[2]; - /* v1 end */ -// /* - unsigned char read_dqs_delay[16]; - unsigned char read_dq_bit_delay[72]; - unsigned short write_dqs_delay[16]; -// */ - unsigned short write_dq_bit_delay[72]; - unsigned short read_dqs_gate_delay[16]; - unsigned char soc_bit_vref[36]; - unsigned char dram_bit_vref[32]; - ///* - unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq - unsigned char dfi_mrl; - unsigned char dfi_hwtmrl; - unsigned char ARdPtrInitVal; - unsigned char retraining[16]; - retraining_set_t retraining_extra_set_t; //override read bit delay }ddr_set_t; @@ -6739,30 +6767,23 @@ int do_ddr_test_pwm_bdlr (cmd_tbl_t *cmdtp, int flag, int argc, char * const arg }while(count<loop); printf("\nDDR_set EE_voltage %d bdlr_100_average %d bdlr_100_min %d bdlr_100_max %d count %d",pwm_voltage_table_ee[to-1][1], bdlr_100_average,bdlr_100_min,bdlr_100_max,count); - - } - - - - return 1; - } int printf_log(char log_level,const char * fmt,...) { -if (log_level<1) -{ -va_list args; -va_start(args,fmt); -vprintf(fmt,args); // -va_end(args); - return 0; -} -else - return 1; + if (log_level<1) + { + va_list args; + va_start(args,fmt); + vprintf(fmt,args); // + va_end(args); + return 0; + } + else + return 1; } int do_read_ddr_training_data(char log_level,ddr_set_t *ddr_set_t_p) { @@ -6779,325 +6800,326 @@ int do_read_ddr_training_data(char log_level,ddr_set_t *ddr_set_t_p) for (loop = 0; loop <MESON_CPU_CHIP_ID_SIZE; loop++) //update chip id { - ddr_sha.sha_chip_id[loop]=global_chip_id[loop]; + ddr_sha.sha_chip_id[loop]=global_chip_id[loop]; } -{ + { uint16_t dq_bit_delay[72]; unsigned char t_count=0; - uint16_t delay_org=0; - uint16_t delay_temp=0; - uint32_t add_offset=0; + uint16_t delay_org=0; + uint16_t delay_temp=0; + uint32_t add_offset=0; dwc_ddrphy_apb_wr(0xd0000,0x0); bdlr_100step=get_bdlr_100step(global_ddr_clk); ui_1_32_100step=(1000000*100/(global_ddr_clk*2*32)); - - { - ddr_set_t_p->ARdPtrInitVal=0; - printf_log(log_level,"\n ARdPtrInitVal"); - add_offset=((0<<20)|(0<<16)|(0<<12)|(0x2e)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - ddr_set_t_p->ARdPtrInitVal=delay_org; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); - - printf_log(log_level,"\n dfimrl0 dfimrl1 dfimrl2 dfimrl3 HwtMRL"); - add_offset=((0<<20)|(1<<16)|(0<<12)|(0x20)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - ddr_set_t_p->dfi_mrl=delay_org; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); - add_offset=((0<<20)|(1<<16)|(1<<12)|(0x20)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",1,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); - add_offset=((0<<20)|(1<<16)|(2<<12)|(0x20)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",2,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); - add_offset=((0<<20)|(1<<16)|(3<<12)|(0x20)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",3,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); - add_offset=((0<<20)|(2<<16)|(0<<12)|(0x20)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - - ddr_set_t_p->dfi_hwtmrl=delay_org; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); - } - { - printf_log(log_level,"\n count_index delay_value register_add register_value \n "); - printf_log(log_level,"\n address delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6 is coarse --step==1UI",ui_1_32_100step); - for (t_count=0;t_count<10;t_count++) - { - add_offset=((0<<20)|(0<<16)|(t_count<<12)|(0x80)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); - ddr_set_t_p->ac_trace_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - } - { - printf_log(log_level,"\n tdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-9 is coarse --step==1UI",ui_1_32_100step); - for (t_count=0;t_count<16;t_count++) + uint32_t ps=0; + for (ps=0;ps<2;ps++) { - add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0xd0+(t_count/8)+((t_count%2)<<8))); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); + { + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal=0; + printf_log(log_level,"\n ARdPtrInitVal ps=%d",ps); + add_offset=((ps<<20)|(2<<16)|(0<<12)|(0x2e)); + delay_org=dwc_ddrphy_apb_rd(add_offset); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal=delay_org; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); + + printf_log(log_level,"\n dfimrl0 dfimrl1 dfimrl2 dfimrl3 HwtMRL ps=%d",ps); + add_offset=((ps<<20)|(1<<16)|(0<<12)|(0x20)); + delay_org=dwc_ddrphy_apb_rd(add_offset); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl=delay_org; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); + add_offset=((ps<<20)|(1<<16)|(1<<12)|(0x20)); + delay_org=dwc_ddrphy_apb_rd(add_offset); + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",1,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); + add_offset=((ps<<20)|(1<<16)|(2<<12)|(0x20)); + delay_org=dwc_ddrphy_apb_rd(add_offset); + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",2,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); + add_offset=((ps<<20)|(1<<16)|(3<<12)|(0x20)); + delay_org=dwc_ddrphy_apb_rd(add_offset); + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",3,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); + add_offset=((ps<<20)|(2<<16)|(0<<12)|(0x20)); + delay_org=dwc_ddrphy_apb_rd(add_offset); + + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl=delay_org; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); + } + { + printf_log(log_level,"\n count_index delay_value register_add register_value ps=%d\n ",ps); + printf_log(log_level,"\n address delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6 is coarse --step==1UI ps=%d",ui_1_32_100step,ps); + for (t_count=0;t_count<10;t_count++) + { + add_offset=((ps<<20)|(0<<16)|(t_count<<12)|(0x80)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_org=dq_bit_delay[t_count]; + delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + } + { + printf_log(log_level,"\n tdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-9 is coarse --step==1UI ps=%d",ui_1_32_100step,ps); + for (t_count=0;t_count<16;t_count++) + { + add_offset=((ps<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0xd0+(t_count/8)+((t_count%2)<<8))); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_org=dq_bit_delay[t_count]; + delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); - ddr_set_t_p->write_dqs_delay[t_count]=delay_temp; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - } - { - printf_log(log_level,"\n rxdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI,no coarse",ui_1_32_100step); - for (t_count=0;t_count<16;t_count++) - { - add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x8c+(t_count/8)+((t_count%2)<<8))); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); - ddr_set_t_p->read_dqs_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - } - { - printf_log(log_level,"\n write dq_bit delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-8 is coarse --step==1U",ui_1_32_100step); - for (t_count=0;t_count<72;t_count++) + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + } { - add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0xc0+((t_count%9)<<8)+(t_count/36))); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); + printf_log(log_level,"\n rxdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI,no coarse ps=%d",ui_1_32_100step,ps); + for (t_count=0;t_count<16;t_count++) + { + add_offset=((ps<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x8c+(t_count/8)+((t_count%2)<<8))); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_org=dq_bit_delay[t_count]; + delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + } + { + printf_log(log_level,"\n write dq_bit delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-8 is coarse --step==1U ps=%d",ui_1_32_100step,ps); + for (t_count=0;t_count<72;t_count++) + { + add_offset=((ps<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0xc0+((t_count%9)<<8)+(t_count/36))); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_org=dq_bit_delay[t_count]; + delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); - ddr_set_t_p->write_dq_bit_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } } - } - { - printf_log(log_level,"\n read dq_bit delay * BDLRx100==%d ps bit0-4 fine tune --step==bdlr step size about 5ps,no coarse",bdlr_100step); - for (t_count=0;t_count<72;t_count++) - { - add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0x68+((t_count%9)<<8)+(t_count/36))); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=((delay_org&0x3f)); + { + printf_log(log_level,"\n read dq_bit delay * BDLRx100==%d ps bit0-4 fine tune --step==bdlr step size about 5ps,no coarse ps=%d",bdlr_100step,ps); + for (t_count=0;t_count<72;t_count++) + { + add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0x68+((t_count%9)<<8)+(t_count/36))); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_org=dq_bit_delay[t_count]; + delay_temp=((delay_org&0x3f)); - ddr_set_t_p->read_dq_bit_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - } - { - printf_log(log_level,"\n read dqs gate delay * 1/32UIx100==%d ps bit0-4 fine tune ,bit 6-10 is coarse",ui_1_32_100step); - for (t_count=0;t_count<16;t_count++) - { - add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x80+(t_count/8)+((t_count%2)<<8))); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + } + { + printf_log(log_level,"\n read dqs gate delay * 1/32UIx100==%d ps bit0-4 fine tune ,bit 6-10 is coarse ps=%d",ui_1_32_100step,ps); + for (t_count=0;t_count<16;t_count++) + { + add_offset=((ps<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x80+(t_count/8)+((t_count%2)<<8))); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_org=dq_bit_delay[t_count]; + delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); - ddr_set_t_p->read_dqs_gate_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } - printf_log(log_level,"\n soc vref : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345"); - //((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value) - uint32_t vref_t_count=0; - for (t_count=0;t_count<72;t_count++) - {//add normal vref0---vrefDac0 for just 1->x transitions - add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x40)); + printf_log(log_level,"\n soc vref : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345 ps=%d",ps); + //((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value) + uint32_t vref_t_count=0; + for (t_count=0;t_count<72;t_count++) + {//add normal vref0---vrefDac0 for just 1->x transitions + add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x40)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_org=dq_bit_delay[t_count]; + delay_temp=((delay_org)); + if (t_count<35) + { + vref_t_count=((((t_count%36)/9)*8)+(t_count%9)); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[vref_t_count]=delay_temp; + } + if ((t_count%9) == 8) + { + vref_t_count=32+((((t_count%36)/9))); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[vref_t_count]=delay_temp; + } + + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + printf_log(log_level,"\n soc vref-dfe dac1 0--->x : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345 ps=%d",ps); + for (t_count=0;t_count<72;t_count++) + { //add dfe vref1---vrefDac1 for just 0->x transitions + add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x30)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_org=dq_bit_delay[t_count]; + delay_temp=((delay_org)); + if (t_count<35) + { + vref_t_count=((((t_count%36)/9)*8)+(t_count%9)); + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count]=delay_temp; + } + if ((t_count%9) == 8) + { + vref_t_count=32+((((t_count%36)/9))); + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count]=delay_temp; + } + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + printf_log(log_level,"\n dram vref : lpddr4-- VREF = VDDQ*(0. + VrefDAC0[6:0]*0. DDR4 --VREF = VDDQ*(0. + VrefDAC0[6:0]*0. ps=%d",ps); + add_offset=((0<<20)|(1<<16)|(0<<12)|(0x082)); + delay_temp=dwc_ddrphy_apb_rd(add_offset); + for (t_count=0;t_count<32;t_count++) + { + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[t_count]=delay_temp; + + // printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_temp); + } + #if 0 + // if(over_ride_index ==DMC_TEST_WINDOW_INDEX_RETRAINING) + { // if (read_write==REGISTER_READ) + for (t_count=0;t_count<4;t_count++) + { ddr_set_t_p->retraining[4*t_count+0]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))&0xff; //PptCtlStatic + ddr_set_t_p->retraining[4*t_count+1]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))>>8; //PptCtlStatic + ddr_set_t_p->retraining[4*t_count+2]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xae)); //PptDqsCntInvTrnTg0 ps0 rank0 lane 0-3 + ddr_set_t_p->retraining[4*t_count+3]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaf)); //PptDqsCntInvTrnTg0 ps0 rank1 lane 0-3 + } + } + #endif + #if 1 //add for skip training + printf_log(log_level,"\n extra retraining setting. ps=%d",ps); + t_count=0; + add_offset=(0<<20)|(2<<16)|(0<<12)|(0xcb); dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=((delay_org)); - if (t_count<35) + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + + for (t_count=0;t_count<4;t_count++) { - vref_t_count=((((t_count%36)/9)*8)+(t_count%9)); - ddr_set_t_p->soc_bit_vref[vref_t_count]=delay_temp; + add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0xaa)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); } - if ((t_count%9) == 8) + for (t_count=0;t_count<4;t_count++) { - vref_t_count=32+((((t_count%36)/9))); - ddr_set_t_p->soc_bit_vref[vref_t_count]=delay_temp; + add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0x62)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); } - - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - printf_log(log_level,"\n soc vref-dfe dac1 0--->x : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345"); - for (t_count=0;t_count<72;t_count++) - { //add dfe vref1---vrefDac1 for just 0->x transitions - add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x30)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=((delay_org)); - if (t_count<35) + for (t_count=0;t_count<4;t_count++) { - vref_t_count=((((t_count%36)/9)*8)+(t_count%9)); - ddr_set_t_p->retraining_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count]=delay_temp; + add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0x01)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); } - if ((t_count%9) == 8) + for (t_count=0;t_count<4;t_count++) { - vref_t_count=32+((((t_count%36)/9))); - ddr_set_t_p->retraining_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count]=delay_temp; + add_offset=((ps<<20)|(1<<16)|(t_count<<12)|(0x43)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); } - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - printf_log(log_level,"\n dram vref : lpddr4-- VREF = VDDQ*(0. + VrefDAC0[6:0]*0. DDR4 --VREF = VDDQ*(0. + VrefDAC0[6:0]*0."); - add_offset=((0<<20)|(1<<16)|(0<<12)|(0x082)); - delay_temp=dwc_ddrphy_apb_rd(add_offset); - for (t_count=0;t_count<32;t_count++) - { - ddr_set_t_p->dram_bit_vref[t_count]=delay_temp; - - // printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_temp); - } - - // if(over_ride_index ==DMC_TEST_WINDOW_INDEX_RETRAINING) - { // if (read_write==REGISTER_READ) - for (t_count=0;t_count<4;t_count++) - { ddr_set_t_p->retraining[4*t_count+0]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))&0xff; //PptCtlStatic - ddr_set_t_p->retraining[4*t_count+1]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))>>8; //PptCtlStatic - ddr_set_t_p->retraining[4*t_count+2]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xae)); //PptDqsCntInvTrnTg0 ps0 rank0 lane 0-3 - ddr_set_t_p->retraining[4*t_count+3]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaf)); //PptDqsCntInvTrnTg0 ps0 rank1 lane 0-3 + for (t_count=0;t_count<4;t_count++) + { + //t_count=0; + add_offset=((ps<<20)|(1<<16)|(t_count<<12)|(0xae)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); } + for (t_count=0;t_count<4;t_count++) + { + //t_count=0; + add_offset=((ps<<20)|(1<<16)|(t_count<<12)|(0xaf)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + //for(t_count=0;t_count<4;t_count++) + { + t_count=0; + add_offset=((ps<<20)|(2<<16)|(t_count<<12)|(0xb2)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + for (t_count=1;t_count<9;t_count++) + { + //t_count=0; + add_offset=((ps<<20)|(9<<16)|(0<<12)|(0x200)|t_count); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[t_count]=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + { + t_count=0; + add_offset=((ps<<20)|(2<<16)|(t_count<<12)|(0x7c)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + { + t_count=0; + add_offset=((ps<<20)|(2<<16)|(t_count<<12)|(0x7d)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + { + t_count=0; + add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x77)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + { + t_count=0; + add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x72)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + { + t_count=0; + add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x73)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + { + t_count=0; + add_offset=((0<<20)|(4<<16)|(t_count<<12)|(0xfd)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + { + t_count=0; + add_offset=((0<<20)|(4<<16)|(t_count<<12)|(0xc0)); + dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); + delay_temp=dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23=delay_temp; + printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + } + //dwc_ddrphy_apb_wr((ps<<20)|(9<<16)|(0<<12)|(0x28), 0); // csr_PhyInLP3_ADDR + #endif + } } - - #if 1 //add for skip training - printf_log(log_level,"\n extra retraining setting."); - t_count=0; - add_offset=(0<<20)|(2<<16)|(0<<12)|(0xcb); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_pllctrl3=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - - for (t_count=0;t_count<4;t_count++) - { - add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0xaa)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_pptctlstatic[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - for (t_count=0;t_count<4;t_count++) - { - add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0x62)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_trainingincdecdtsmen[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - for (t_count=0;t_count<4;t_count++) - { - add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0x01)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_tsmbyte0[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - for (t_count=0;t_count<4;t_count++) - { - add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0x43)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_dqsrcvcntrl[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - for (t_count=0;t_count<4;t_count++) - { - //t_count=0; - add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0xae)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_pptdqscntinvtrntg0[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - for (t_count=0;t_count<4;t_count++) - { - //t_count=0; - add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0xaf)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_pptdqscntinvtrntg1[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - //for(t_count=0;t_count<4;t_count++) - { - t_count=0; - add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0xb2)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_vrefinglobal=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - for (t_count=1;t_count<9;t_count++) - { - //t_count=0; - add_offset=((0<<20)|(9<<16)|(0<<12)|(0x200)|t_count); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_seq0bgpr[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - { - t_count=0; - add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x7c)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_dllgainctl=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - { - t_count=0; - add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x7d)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_dlllockpara=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - { - t_count=0; - add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x77)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_hwtcamode=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - { - t_count=0; - add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x72)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_hwtlpcsena=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - { - t_count=0; - add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x73)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_hwtlpcsenb=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - { - t_count=0; - add_offset=((0<<20)|(4<<16)|(t_count<<12)|(0xfd)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_acsmctrl13=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - { - t_count=0; - add_offset=((0<<20)|(4<<16)|(t_count<<12)|(0xc0)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->retraining_extra_set_t.csr_acsmctrl23=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - //dwc_ddrphy_apb_wr((ps<<20)|(9<<16)|(0<<12)|(0x28), 0); // csr_PhyInLP3_ADDR - #endif - -} - return 1; } int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -7106,6 +7128,7 @@ int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, cha // if(!argc) // goto DDR_TUNE_DQS_START; int i=0; + unsigned int ps=0; printf("\nargc== 0x%08x\n", argc); for (i = 0;i<argc;i++) printf("\nargv[%d]=%s\n",i,argv[i]); @@ -7113,7 +7136,7 @@ int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, cha ddr_set_t_p=(ddr_set_t *)(ddr_set_t_p_arrary); do_read_ddr_training_data(0,ddr_set_t_p); -{ + { uint32_t count=0; uint32_t reg_add_offset=0; uint16_t reg_value=0; @@ -7178,7 +7201,7 @@ int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, cha } } // ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level); -} + } printf("\n {"); @@ -7199,9 +7222,15 @@ int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, cha printf("\n.HdtCtrl=0x%08x,// %d",ddr_set_t_p->HdtCtrl,ddr_set_t_p->HdtCtrl); printf("\n.dram_rank_config=0x%08x,// %d",ddr_set_t_p->dram_rank_config,ddr_set_t_p->dram_rank_config); printf("\n.diagnose=0x%08x,// %d",ddr_set_t_p->diagnose,ddr_set_t_p->diagnose); - printf("\n.imem_load_addr=0x%08x,// %d",ddr_set_t_p->imem_load_addr,ddr_set_t_p->imem_load_addr); - printf("\n.dmem_load_addr=0x%08x,// %d",ddr_set_t_p->dmem_load_addr,ddr_set_t_p->dmem_load_addr); - printf("\n.imem_load_size=0x%08x,// %d",ddr_set_t_p->imem_load_size,ddr_set_t_p->imem_load_size); + //printf("\n.imem_load_addr=0x%08x,// %d",ddr_set_t_p->imem_load_addr,ddr_set_t_p->imem_load_addr); + //printf("\n.dmem_load_addr=0x%08x,// %d",ddr_set_t_p->dmem_load_addr,ddr_set_t_p->dmem_load_addr); + //printf("\n.imem_load_size=0x%08x,// %d",ddr_set_t_p->imem_load_size,ddr_set_t_p->imem_load_size); + printf("\n.soc_data_drv_ohm_ps1=0x%08x,// %d",ddr_set_t_p->soc_data_drv_ohm_ps1,ddr_set_t_p->soc_data_drv_ohm_ps1); + printf("\n.dram_data_drv_ohm_ps1=0x%08x,// %d",ddr_set_t_p->dram_data_drv_ohm_ps1,ddr_set_t_p->dram_data_drv_ohm_ps1); + printf("\n.soc_data_odt_ohm_ps1=0x%08x,// %d",ddr_set_t_p->soc_data_odt_ohm_ps1,ddr_set_t_p->soc_data_odt_ohm_ps1); + printf("\n.dram_data_odt_ohm_ps1=0x%08x,// %d",ddr_set_t_p->dram_data_odt_ohm_ps1,ddr_set_t_p->dram_data_odt_ohm_ps1); + printf("\n.dram_data_wr_odt_ohm_ps1=0x%08x,// %d",ddr_set_t_p->dram_data_wr_odt_ohm_ps1,ddr_set_t_p->dram_data_wr_odt_ohm_ps1); + printf("\n.dmem_load_size=0x%08x,// %d",ddr_set_t_p->dmem_load_size,ddr_set_t_p->dmem_load_size); printf("\n.ddr_base_addr=0x%08x,// %d",ddr_set_t_p->ddr_base_addr,ddr_set_t_p->ddr_base_addr); printf("\n.ddr_start_offset=0x%08x,// %d",ddr_set_t_p->ddr_start_offset,ddr_set_t_p->ddr_start_offset); @@ -7361,65 +7390,71 @@ int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, cha printf("\n.dram_rtt_nom_wr_park[0]=0x%08x,// %d",ddr_set_t_p->dram_rtt_nom_wr_park[0],ddr_set_t_p->dram_rtt_nom_wr_park[0]); printf("\n.dram_rtt_nom_wr_park[1]=0x%08x,// %d",ddr_set_t_p->dram_rtt_nom_wr_park[1],ddr_set_t_p->dram_rtt_nom_wr_park[1]); printf("\n.ddr_func=0x%08x,// %d",ddr_set_t_p->ddr_func,ddr_set_t_p->ddr_func); - - for ( temp_count=0;temp_count<16;temp_count++) - printf("\n.read_dqs_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->read_dqs_delay[temp_count],ddr_set_t_p->read_dqs_delay[temp_count]); - for ( temp_count=0;temp_count<72;temp_count++) - printf("\n.read_dq_bit_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->read_dq_bit_delay[temp_count],ddr_set_t_p->read_dq_bit_delay[temp_count]); - for ( temp_count=0;temp_count<16;temp_count++) - //printf("\n.write_dqs_delay[%d]=%d,",temp_count,ddr_set_t_p->write_dqs_delay[temp_count]); - printf("\n.write_dqs_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->write_dqs_delay[temp_count],ddr_set_t_p->write_dqs_delay[temp_count]); - for ( temp_count=0;temp_count<72;temp_count++) - //printf("\n.write_dq_bit_delay[%d]=%d,",temp_count,ddr_set_t_p->write_dq_bit_delay[temp_count]); - printf("\n.write_dq_bit_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->write_dq_bit_delay[temp_count],ddr_set_t_p->write_dq_bit_delay[temp_count]); - for ( temp_count=0;temp_count<16;temp_count++) - //printf("\n.read_dqs_gate_delay[%d]=%d,",temp_count,ddr_set_t_p->read_dqs_gate_delay[temp_count]); - printf("\n.read_dqs_gate_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->read_dqs_gate_delay[temp_count],ddr_set_t_p->read_dqs_gate_delay[temp_count]); - for ( temp_count=0;temp_count<36;temp_count++) - //printf("\n.soc_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->soc_bit_vref[temp_count]); - printf("\n.soc_bit_vref[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->soc_bit_vref[temp_count],ddr_set_t_p->soc_bit_vref[temp_count]); - for ( temp_count=0;temp_count<36;temp_count++) - //printf("\n.soc_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->soc_bit_vref[temp_count]); - printf("\n.retraining_extra_set_t.csr_soc_vref_dac1_dfe[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining_extra_set_t.csr_soc_vref_dac1_dfe[temp_count],ddr_set_t_p->retraining_extra_set_t.csr_soc_vref_dac1_dfe[temp_count]); - //printf("\n.soc_bit_vref[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->soc_bit_vref[temp_count],ddr_set_t_p->soc_bit_vref[temp_count]); - for ( temp_count=0;temp_count<32;temp_count++) - //printf("\n.dram_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->dram_bit_vref[temp_count]); - printf("\n.dram_bit_vref[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->dram_bit_vref[temp_count],ddr_set_t_p->dram_bit_vref[temp_count]); - - //ddr_set_t_p->dq_dqs_delay_flag=0xff; - printf("\n.rever3=0x%08x,// %d",ddr_set_t_p->rever3,ddr_set_t_p->rever3); - printf("\n.dfi_mrl=0x%08x,// %d",ddr_set_t_p->dfi_mrl,ddr_set_t_p->dfi_mrl); - printf("\n.dfi_hwtmrl=0x%08x,// %d",ddr_set_t_p->dfi_hwtmrl,ddr_set_t_p->dfi_hwtmrl); - printf("\n.ARdPtrInitVal=0x%08x,// %d",ddr_set_t_p->ARdPtrInitVal,ddr_set_t_p->ARdPtrInitVal); - + for ( ps=0;ps<2;ps++) + { + for ( temp_count=0;temp_count<10;temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].ac_trace_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count]); + + for ( temp_count=0;temp_count<16;temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count]); + for ( temp_count=0;temp_count<72;temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].read_dq_bit_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count]); + for ( temp_count=0;temp_count<16;temp_count++) + //printf("\n.write_dqs_delay[%d]=%d,",temp_count,ddr_set_t_p->write_dqs_delay[temp_count]); + printf("\n.cfg_ddr_training_delay_ps[%d].write_dqs_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count]); + for ( temp_count=0;temp_count<72;temp_count++) + //printf("\n.write_dq_bit_delay[%d]=%d,",temp_count,ddr_set_t_p->write_dq_bit_delay[temp_count]); + printf("\n.cfg_ddr_training_delay_ps[%d].write_dq_bit_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count]); + for ( temp_count=0;temp_count<16;temp_count++) + //printf("\n.read_dqs_gate_delay[%d]=%d,",temp_count,ddr_set_t_p->read_dqs_gate_delay[temp_count]); + printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_gate_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count]); + for ( temp_count=0;temp_count<36;temp_count++) + //printf("\n.soc_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->soc_bit_vref[temp_count]); + printf("\n.cfg_ddr_training_delay_ps[%d].soc_bit_vref[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count]); + for ( temp_count=0;temp_count<36;temp_count++) + //printf("\n.soc_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->soc_bit_vref[temp_count]); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[temp_count],ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[temp_count]); + //printf("\n.soc_bit_vref[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->soc_bit_vref[temp_count],ddr_set_t_p->soc_bit_vref[temp_count]); + for ( temp_count=0;temp_count<32;temp_count++) + //printf("\n.dram_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->dram_bit_vref[temp_count]); + printf("\n.cfg_ddr_training_delay_ps[%d].dram_bit_vref[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count]); + + //ddr_set_t_p->dq_dqs_delay_flag=0xff; + //printf("\n.rever3=0x%08x,// %d",ddr_set_t_p->rever3,ddr_set_t_p->rever3); + printf("\n.cfg_ddr_training_delay_ps[%d].dfi_mrl=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl); + printf("\n.cfg_ddr_training_delay_ps[%d].dfi_hwtmrl=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl); + printf("\n.cfg_ddr_training_delay_ps[%d].ARdPtrInitVal=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal); + + printf("\n.cfg_ddr_training_delay_ps[%d].csr_vrefinglobal=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal); + for ( temp_count=0;temp_count<4;temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].csr_dqsrcvcntrl[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[temp_count]); + for ( temp_count=0;temp_count<4;temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].csr_pptdqscntinvtrntg0[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[temp_count]); + for ( temp_count=0;temp_count<4;temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].csr_pptdqscntinvtrntg1[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[temp_count]); + for ( temp_count=0;temp_count<9;temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].csr_seq0bgpr[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[temp_count]); + printf("\n.cfg_ddr_training_delay_ps[%d].csr_dllgainctl=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl); + printf("\n.cfg_ddr_training_delay_ps[%d].csr_dlllockpara=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara); + } + #if 0 for ( temp_count=0;temp_count<16;temp_count++) //printf("\n.dram_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->dram_bit_vref[temp_count]); printf("\n.retraining[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining[temp_count],ddr_set_t_p->retraining[temp_count]); - - printf("\n.retraining_extra_set_t.csr_pllctrl3=0x%08x,// %d",ddr_set_t_p->retraining_extra_set_t.csr_pllctrl3,ddr_set_t_p->retraining_extra_set_t.csr_pllctrl3); + #endif + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_pllctrl3=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3); for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.retraining_extra_set_t.csr_pptctlstatic[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining_extra_set_t.csr_pptctlstatic[temp_count],ddr_set_t_p->retraining_extra_set_t.csr_pptctlstatic[temp_count]); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[temp_count],ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[temp_count]); for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.retraining_extra_set_t.csr_trainingincdecdtsmen[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining_extra_set_t.csr_trainingincdecdtsmen[temp_count],ddr_set_t_p->retraining_extra_set_t.csr_trainingincdecdtsmen[temp_count]); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[temp_count],ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[temp_count]); for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.retraining_extra_set_t.csr_tsmbyte0[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining_extra_set_t.csr_tsmbyte0[temp_count],ddr_set_t_p->retraining_extra_set_t.csr_tsmbyte0[temp_count]); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[temp_count],ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[temp_count]); - printf("\n.retraining_extra_set_t.csr_vrefinglobal=0x%08x,// %d",ddr_set_t_p->retraining_extra_set_t.csr_vrefinglobal,ddr_set_t_p->retraining_extra_set_t.csr_vrefinglobal); - for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.retraining_extra_set_t.csr_dqsrcvcntrl[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining_extra_set_t.csr_dqsrcvcntrl[temp_count],ddr_set_t_p->retraining_extra_set_t.csr_dqsrcvcntrl[temp_count]); - for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.retraining_extra_set_t.csr_pptdqscntinvtrntg0[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining_extra_set_t.csr_pptdqscntinvtrntg0[temp_count],ddr_set_t_p->retraining_extra_set_t.csr_pptdqscntinvtrntg0[temp_count]); - for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.retraining_extra_set_t.csr_pptdqscntinvtrntg1[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining_extra_set_t.csr_pptdqscntinvtrntg1[temp_count],ddr_set_t_p->retraining_extra_set_t.csr_pptdqscntinvtrntg1[temp_count]); - for ( temp_count=0;temp_count<9;temp_count++) - printf("\n.retraining_extra_set_t.csr_seq0bgpr[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining_extra_set_t.csr_seq0bgpr[temp_count],ddr_set_t_p->retraining_extra_set_t.csr_seq0bgpr[temp_count]); - printf("\n.retraining_extra_set_t.csr_dllgainctl=0x%08x,// %d",ddr_set_t_p->retraining_extra_set_t.csr_dllgainctl,ddr_set_t_p->retraining_extra_set_t.csr_dllgainctl); - printf("\n.retraining_extra_set_t.csr_dlllockpara=0x%08x,// %d",ddr_set_t_p->retraining_extra_set_t.csr_dlllockpara,ddr_set_t_p->retraining_extra_set_t.csr_dlllockpara); - printf("\n.retraining_extra_set_t.csr_hwtcamode=0x%08x,// %d",ddr_set_t_p->retraining_extra_set_t.csr_hwtcamode,ddr_set_t_p->retraining_extra_set_t.csr_hwtcamode); - printf("\n.retraining_extra_set_t.csr_hwtlpcsena=0x%08x,// %d",ddr_set_t_p->retraining_extra_set_t.csr_hwtlpcsena,ddr_set_t_p->retraining_extra_set_t.csr_hwtlpcsena); - printf("\n.retraining_extra_set_t.csr_hwtlpcsenb=0x%08x,// %d",ddr_set_t_p->retraining_extra_set_t.csr_hwtlpcsenb,ddr_set_t_p->retraining_extra_set_t.csr_hwtlpcsenb); - printf("\n.retraining_extra_set_t.csr_acsmctrl13=0x%08x,// %d",ddr_set_t_p->retraining_extra_set_t.csr_acsmctrl13,ddr_set_t_p->retraining_extra_set_t.csr_acsmctrl13); - printf("\n.retraining_extra_set_t.csr_acsmctrl23=0x%08x,// %d",ddr_set_t_p->retraining_extra_set_t.csr_acsmctrl23,ddr_set_t_p->retraining_extra_set_t.csr_acsmctrl23); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtcamode=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23); printf("\n},\n"); @@ -7576,8 +7611,7 @@ int do_ddr_fastboot_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar uint32_t write_size=0; write_size=((ddr_set_size+SHA256_SUM_LEN+MESON_CPU_CHIP_ID_SIZE+511)/512)*512; do_read_ddr_training_data(1,ddr_set_t_p); -{ - + { dwc_ddrphy_apb_wr(0xd0000,0x0); char dmc_test_worst_window_rx=0; @@ -7589,15 +7623,14 @@ int do_ddr_fastboot_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar dmc_test_worst_window_tx=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0x0c2)); dmc_test_worst_window_rx=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0x0c3)); if (dmc_test_worst_window_tx>30) - dmc_test_worst_window_tx=30; + dmc_test_worst_window_tx=30; if (dmc_test_worst_window_rx>30) - dmc_test_worst_window_rx=30; + dmc_test_worst_window_rx=30; // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x1c2),t4_write_worst_margin_rank1); // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x1c3),t4_read_worst_margin_rank1); ddr_set_t_p->fast_boot[1]=(((dmc_test_worst_window_tx/2)<<4))|(((dmc_test_worst_window_rx/2))); - } - -} + } + } //store ddr_parameter write 0x77f81cf0 0x300 @@ -7654,7 +7687,18 @@ int do_ddr_fastboot_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar #endif ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add-SHA256_SUM_LEN),write_size); } - + #if 0 + serial_puts("\n"); + for ( count=0;count<(sizeof(ddr_set_t));) { + //printf("\n%08x %08x",count,(rd_reg((uint64_t)(ddr_set_t_p)+(uint64_t)count))); + serial_puts("\n"); + serial_put_hex(count,32); + serial_puts(" "); + serial_put_hex(rd_reg((uint64_t)(p_dev->p_ddrs)+(uint64_t)count),32); + count=count+4; + } + serial_puts("\n"); + #endif return 1; } @@ -9580,6 +9624,7 @@ void dwc_window_reg_after_training_update_increas(char over_ride_index,uint32_t char temp_test_index_2=0; char temp_count_4=0; char temp_count_2=0; + #if 0 if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { temp_test_index_2=DMC_TEST_WINDOW_INDEX_TXDQDLY; @@ -9603,6 +9648,7 @@ void dwc_window_reg_after_training_update_increas(char over_ride_index,uint32_t } */ } + #endif if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { temp_test_index_2=DMC_TEST_WINDOW_INDEX_RXPBDLY; |