summaryrefslogtreecommitdiff
authorLuan Yuan <luan.yuan@amlogic.com>2019-11-04 08:50:47 (GMT)
committer Xindong Xu <xindong.xu@amlogic.com>2019-11-28 01:39:53 (GMT)
commitccc5c3bb0b9e46e90596129cad3e3f0acc722fc7 (patch)
treee14bf009ffebe24c21150ae41a88628300b33462
parentfea22d89437a28d3d9e4b2ec73b6c34156f83bb5 (diff)
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uboot-ccc5c3bb0b9e46e90596129cad3e3f0acc722fc7.tar.gz
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uboot: add anning(s805y) config. [1/3]
PD#SWPL-16193 Problem: add anning(s805y) config. Solution: add anning(s805y) config. Verify: verify by anning Change-Id: I2aadc496117c942e85434af05191e0cb9e9eb713 Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
Diffstat
-rwxr-xr-xboard/amlogic/Kconfig8
-rw-r--r--board/amlogic/configs/gxl_p244_v1.h632
-rw-r--r--board/amlogic/defconfigs/gxl_p244_v1_defconfig6
-rw-r--r--board/amlogic/gxl_p244_v1/Kconfig22
-rw-r--r--board/amlogic/gxl_p244_v1/Makefile2
-rw-r--r--board/amlogic/gxl_p244_v1/aml-user-key.sig29
-rw-r--r--board/amlogic/gxl_p244_v1/eth_setup.c50
-rw-r--r--board/amlogic/gxl_p244_v1/firmware/board_init.c28
-rw-r--r--board/amlogic/gxl_p244_v1/firmware/power.c185
-rw-r--r--board/amlogic/gxl_p244_v1/firmware/ramdump.c69
-rw-r--r--board/amlogic/gxl_p244_v1/firmware/ramdump.h99
-rw-r--r--board/amlogic/gxl_p244_v1/firmware/scp_task/dvfs_board.c192
-rw-r--r--board/amlogic/gxl_p244_v1/firmware/scp_task/dvfs_board.h23
-rw-r--r--board/amlogic/gxl_p244_v1/firmware/scp_task/pwr_ctrl.c310
-rw-r--r--board/amlogic/gxl_p244_v1/firmware/timing.c694
-rw-r--r--board/amlogic/gxl_p244_v1/gxl_p244_v1.c644
-rw-r--r--board/amlogic/gxl_p244_v1/lcd.c248
17 files changed, 3241 insertions, 0 deletions
diff --git a/board/amlogic/Kconfig b/board/amlogic/Kconfig
index a86c06b..a90d41c 100755
--- a/board/amlogic/Kconfig
+++ b/board/amlogic/Kconfig
@@ -51,6 +51,10 @@ config GXL_P212_V1
bool "Support amlogic gxl p212 board"
default n
+config GXL_P244_V1
+ bool "Support amlogic gxl p244 board"
+ default n
+
config GXL_P281_V1
bool "Support amlogic gxl p281 board"
default n
@@ -346,6 +350,10 @@ if GXL_SEI210_V1
source "board/amlogic/gxl_beast_v1/Kconfig"
endif
+if GXL_P244_V1
+source "board/amlogic/gxl_p244_v1/Kconfig"
+endif
+
if GXL_P281_V1
source "board/amlogic/gxl_p281_v1/Kconfig"
endif
diff --git a/board/amlogic/configs/gxl_p244_v1.h b/board/amlogic/configs/gxl_p244_v1.h
new file mode 100644
index 0000000..ac7d8eb
--- a/dev/null
+++ b/board/amlogic/configs/gxl_p244_v1.h
@@ -0,0 +1,632 @@
+
+/*
+ * board/amlogic/configs/gxl_p244_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXL_P244_V1_H__
+#define __GXL_P244_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1120
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+#define CONFIG_BT_WAKEUP
+#define CONFIG_INSTABOOT
+/* configs for dtb in boot.img */
+//#define DTB_BIND_KERNEL
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/*config irblaster*/
+#define CONFIG_CMD_IRBLASTER 1
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/*a/b update */
+#define CONFIG_CMD_BOOTCTOL_AVB
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "sdr2hdr=0\0" \
+ "usb_burning=update 1000\0" \
+ "otg_device=1\0"\
+ "fdt_high=0x20000000\0"\
+ "lock=10001000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=normal\0"\
+ "page_trace=on\0"\
+ "boot_part=boot\0"\
+ "rpmb_state=0\0"\
+ "Irq_check_en=0\0"\
+ "reboot_mode_android=""normal""\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "colorattribute=444,8bit\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} cvbsmode=${cvbsmode} hdmitx=${cecconfig},${colorattribute} cvbsdrv=${cvbs_drv} irq_check_en=${Irq_check_en} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.veritymode=enforcing androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
+ "setenv bootargs ${bootargs} page_trace=${page_trace};" \
+ "setenv bootargs ${bootargs} androidboot.rpmb_state=${rpmb_state};"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "get_system_as_root_mode;"\
+ "echo system_mode: ${system_mode};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "fi;"\
+ "get_valid_slot;"\
+ "get_avb_mode;"\
+ "echo active_slot: ${active_slot} avb2: ${avb2};"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if test ${avb2} = 0; then "\
+ "if test ${active_slot} = _a; then "\
+ "setenv bootargs ${bootargs} root=/dev/mmcblk0p23;"\
+ "else if test ${active_slot} = _b; then "\
+ "setenv bootargs ${bootargs} root=/dev/mmcblk0p24;"\
+ "fi;fi;"\
+ "fi;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run storeargs; run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "get_valid_slot;"\
+ "echo active_slot: ${active_slot};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale; "\
+ "fi;fi;"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read mac_bt ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac_bt=${mac_bt} androidboot.mac_bt=${mac_bt};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "if keyman read region_code ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=US;"\
+ "fi;"\
+ "if keyman read oemkey ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.oem.key1=${oemkey};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.oem.key1=ATV00104319;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR_CHL_AUTO
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+//#define CONFIG_AML_MTD 1
+/* support for nftl */
+#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+ /*
+ flash/erase operation region on boot1
+ in bytes, 2M by default
+ */
+ //#define CONFIG_EMMC_BOOT1_TOUCH_REGION (0x200000)
+
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+
+/* env checks */
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+//#define CONFIG_AML_GPT
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_AML_MINUI 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "anning"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#ifndef DTB_BIND_KERNEL
+#define CONFIG_UNIFY_KEY_MANAGE 1
+#endif
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+#define CONFIG_MDUMP_COMPRESS 1
+#define CONFIG_EXT4_WRITE 1
+#define CONFIG_CMD_EXT4 1
+#define CONFIG_CMD_EXT4_WRITE 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_MULTI_DTB 1
+
+#define CONFIG_CMD_CHIPID 1
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+//anti-rollback function
+//#define CONFIG_AML_ANTIROLLBACK 1
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+//#define CONFIG_AVB2
+#endif
+
diff --git a/board/amlogic/defconfigs/gxl_p244_v1_defconfig b/board/amlogic/defconfigs/gxl_p244_v1_defconfig
new file mode 100644
index 0000000..d7b2197
--- a/dev/null
+++ b/board/amlogic/defconfigs/gxl_p244_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_P244_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/gxl_p244_v1/Kconfig b/board/amlogic/gxl_p244_v1/Kconfig
new file mode 100644
index 0000000..8404f23
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxl_p244_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_p244_v1"
+
+endif
diff --git a/board/amlogic/gxl_p244_v1/Makefile b/board/amlogic/gxl_p244_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxl_p244_v1/aml-user-key.sig b/board/amlogic/gxl_p244_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/aml-user-key.sig
@@ -0,0 +1,29 @@
+yt}|4B/iֻxn:fޞpdd'tNZ !@ $ -Ȱ 2{^sW`D#@>+bqyd:T8Ο Oh!;z|۽DȄdR!Q_IU6 w>Kox"vp}d,6ψQΆdY<_,R/sL)e'is֭HoyU%a>1&FQ#[ ⁻[޺1 rBRPH
+|݂hTsj9 }n35f3?szc.n%ZJ;.݁8MכE@_ Ji ንf_Zq"i@ctu=~t
+INKBTqa`oԿDřMg>Q/zx_Y;Vyv/U)jp`MY6UؼS)OvWz<Qǯb8ZX`SXQ,ZܳcWj]-̹
+bt
+!R
+^PD{<醎: _|M̃$.<
+M{]$:Z);KrO T\>O@hi9Y
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+q]R2ݐ*"gd,ι
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+V|0'W3ÐC¼7|g6Hxn'33"FUvQ5b
+XE*FEh\bgK~ݻܶFn<LoN?(G𶀖Q3pdq;y "AO̹S욠oI$J6+c1d"ƕ@4lNA)5NTUZ ?L[l1|5^}wc^hD}4ՊW7?)?
+ +Cը
+ Dž,#U
+1pÝަRG0\#Ixybr?' JPLC7L)^ ugd ͤ @&[BEUocs E:OU `V!)}UgM$ c]
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+ғJy8۷kx
+K\E=
+
diff --git a/board/amlogic/gxl_p244_v1/eth_setup.c b/board/amlogic/gxl_p244_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxl_p244_v1/firmware/board_init.c b/board/amlogic/gxl_p244_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+} \ No newline at end of file
diff --git a/board/amlogic/gxl_p244_v1/firmware/power.c b/board/amlogic/gxl_p244_v1/firmware/power.c
new file mode 100644
index 0000000..fce6e3c
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/firmware/power.c
@@ -0,0 +1,185 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxl_p244_v1/firmware/ramdump.c b/board/amlogic/gxl_p244_v1/firmware/ramdump.c
new file mode 100644
index 0000000..4e8e96f
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/firmware/ramdump.c
@@ -0,0 +1,69 @@
+/*
+ * board/amlogic/gxl_p212_v1/firmware/ramdump.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifdef CONFIG_MDUMP_COMPRESS
+#include "ramdump.h"
+
+struct ram_compress_full __ramdump_data = {
+ .store_phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
+ .full_memsize = CONFIG_DDR_TOTAL_SIZE,
+ .section_count = CONFIG_COMPRESS_SECTION,
+ .sections = {
+ {
+ /* memory afer compressed data address */
+ .phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
+ .section_size = CONFIG_DDR_TOTAL_SIZE -
+ CONFIG_COMPRESSED_DATA_ADDR,
+ .section_index = 5,
+ .compress_type = RAM_COMPRESS_NORMAL,
+ },
+ {
+ /* memory in reserved bottom */
+ .phy_addr = (void *)CONFIG_COMPRESS_START_ADDR,
+ .section_size = CONFIG_1ST_RESERVED_SIZE,
+ .section_index = 1,
+ .compress_type = RAM_COMPRESS_SET,
+ .set_value = 0x0,
+ },
+ {
+ /* memory before bl2 */
+ .phy_addr = (void *)CONFIG_1ST_RESERVED_END,
+ .section_size = CONFIG_BL2_IGNORE_ADDR -
+ CONFIG_1ST_RESERVED_END,
+ .section_index = 2,
+ .compress_type = RAM_COMPRESS_NORMAL,
+ },
+ {
+ /* memory in reserved bl2 */
+ .phy_addr = (void *)CONFIG_BL2_IGNORE_ADDR,
+ .section_size = CONFIG_BL2_IGNORE_SIZE,
+ .section_index = 3,
+ .compress_type = RAM_COMPRESS_SET,
+ .set_value = 0x0,
+ },
+ {
+ /* segment 4: normal compress */
+ .phy_addr = (void *)CONFIG_SEG4_ADDR,
+ .section_size = CONFIG_COMPRESSED_DATA_ADDR -
+ CONFIG_SEG4_ADDR,
+ .section_index = 4,
+ .compress_type = RAM_COMPRESS_NORMAL,
+ }
+ },
+};
+#endif /* CONFIG_MDUMP_COMPRESS */
+
diff --git a/board/amlogic/gxl_p244_v1/firmware/ramdump.h b/board/amlogic/gxl_p244_v1/firmware/ramdump.h
new file mode 100644
index 0000000..7df2ebb
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/firmware/ramdump.h
@@ -0,0 +1,99 @@
+/*
+ * board/amlogic/gxl_p212_v1/firmware/ramdump.h
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef __RAM_DUMP_H__
+#define __RAM_DUMP_H__
+
+#include <config.h>
+#ifdef CONFIG_MDUMP_COMPRESS
+#define CONFIG_COMPRESS_SECTION 5
+
+#if CONFIG_COMPRESS_SECTION > 8
+#error ---> CONFIG_COMPRESS_SECTION out of range, max should be 8
+#endif
+/*
+ * Full Memory lay out for RAM compress:
+ *
+ * DDR_TOP -> +--------+
+ * | |
+ * | |
+ * | 5 |
+ * | |
+ * | |
+ * |~~~~~~~~| <- store compressing data
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * COMPRESSED_DATA -> +--------+
+ * | |
+ * | 4 |
+ * | |
+ * BL2_IGNORE_END -> +--------+ -- IGNORE_SIZE
+ * ||||||||||
+ * ||||3|||||
+ * ||||||||||
+ * BL2_IGNORE_ADDR -> +--------+
+ * | |
+ * | 2 |
+ * | |
+ * CONFIG_1ST_RESERVED_END-> +--------+
+ * | |
+ * | 1 |
+ * | |
+ * COMPRESS_START_ADDR -> +--------+
+ */
+#define CONFIG_DDR_TOTAL_SIZE (CONFIG_DDR_SIZE << 20)
+#define CONFIG_COMPRESSED_DATA_ADDR (0x08000000)
+#define CONFIG_COMPRESSED_DATA_ADDR1 (0x08000000)
+
+#define CONFIG_COMPRESS_START_ADDR (0x00000000)
+#define CONFIG_1ST_RESERVED_SIZE (0x00100000)
+#define CONFIG_1ST_RESERVED_END (CONFIG_1ST_RESERVED_SIZE + \
+ CONFIG_COMPRESS_START_ADDR)
+#define CONFIG_BL2_IGNORE_ADDR (0x05000000)
+#define CONFIG_BL2_IGNORE_SIZE (0x00300000)
+#define CONFIG_SEG4_ADDR (CONFIG_BL2_IGNORE_ADDR + \
+ CONFIG_BL2_IGNORE_SIZE)
+
+enum {
+ RAM_COMPRESS_NORMAL = 1,
+ RAM_COMPRESS_COPY = 2,
+ RAM_COMPRESS_SET = 3 /* set ram content to same vale */
+};
+
+struct ram_compress_section {
+ void *phy_addr;
+ unsigned int section_size;
+ unsigned int section_index : 8;
+ unsigned int compress_type : 8;
+ unsigned int set_value : 16;
+};
+
+struct ram_compress_full {
+ void *store_phy_addr;
+ unsigned int full_memsize;
+ unsigned int section_count;
+ struct ram_compress_section sections[CONFIG_COMPRESS_SECTION];
+};
+
+#endif
+#endif /* __RAM_DUMP_H__ */
diff --git a/board/amlogic/gxl_p244_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_p244_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..d1a356c
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,192 @@
+/*
+* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+* *
+This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+* *
+This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+* *
+You should have received a copy of the GNU General Public License along
+* with this program; if not, write to the Free Software Foundation, Inc.,
+* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+* *
+Description:
+*/
+
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+ DVFS(1416000000, 1110+30),
+ //DVFS(1512000000, 1110+30),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_D;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_D = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxl_p244_v1/firmware/scp_task/dvfs_board.h b/board/amlogic/gxl_p244_v1/firmware/scp_task/dvfs_board.h
new file mode 100644
index 0000000..3531bb3
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/firmware/scp_task/dvfs_board.h
@@ -0,0 +1,23 @@
+/*
+* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+* *
+This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+* *
+This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+* *
+You should have received a copy of the GNU General Public License along
+* with this program; if not, write to the Free Software Foundation, Inc.,
+* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+* *
+Description:
+*/
+
+#ifndef __DVFS_BOARD_H__
+extern int pwm_voltage_table[31][2];
+#endif
diff --git a/board/amlogic/gxl_p244_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_p244_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..3aef025
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,310 @@
+/*
+* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+* *
+This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+* *
+This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+* *
+You should have received a copy of the GNU General Public License along
+* with this program; if not, write to the Free Software Foundation, Inc.,
+* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+* *
+Description:
+*/
+
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "dvfs_board.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB \
+ (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD \
+ (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+static struct pwr_op *g_pwr_op;
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage)
+ break;
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table))
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 1 << 25);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ } else {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE);
+ /* reduce power */
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIODV_24*/
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ if (g_pwr_op->exit_reason != 4) {
+ /* bluetooth wakeup */
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 1 << 24);
+ }
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+#ifdef CONFIG_BT_WAKEUP
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+#endif
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1) {
+ cec_node_init();
+ }
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+#ifdef CONFIG_BT_WAKEUP
+ if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+ irq[IRQ_GPIO1] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO4_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+#endif
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+ pwr_op->exit_reason = 0;
+ g_pwr_op = pwr_op;
+}
+
diff --git a/board/amlogic/gxl_p244_v1/firmware/timing.c b/board/amlogic/gxl_p244_v1/firmware/timing.c
new file mode 100644
index 0000000..a2f4892
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/firmware/timing.c
@@ -0,0 +1,694 @@
+
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_240OHM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_0OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+//#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+//#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#else
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#endif
+
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#if (CONFIG_LPDDR_REMAP_SET == LPDDR_DIE_ROW_COL_R14_C9)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#elif (CONFIG_LPDDR_REMAP_SET== LPDDR_DIE_ROW_COL_R13_C10)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#endif /*CONFIG_LPDDR_REMAP_SET*/
+#else
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+#endif /*CONFIG_DDR_TYPE_LPDDR3*/
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+//lpddr3
+ .t_pub_zq0pr = 0x0ca1c, //0x0ca1c, //PUB ZQ0PR //lpddr3
+ .t_pub_zq1pr = 0x1cf3c, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x1cf3c, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+/* 2layer board
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+*/
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+/* 4layer ddr4 */
+ .t_pub_zq0pr = 0x0995d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#else // ddr3 and auto
+/* p212 4layer board ddr3 */
+ .t_pub_zq0pr = 0x5d95d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x5d95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x5d95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#endif
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+///*lpddr3
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune TAKE CARE LPDDR3 ADD/CMD DELAY
+ .t_pub_aclcdlr = 0,
+ .t_pub_acbdlr3 = 0x2020,//0, //CK0 delay fine tune b-3f //lpddr3 tianhe 2016-10-13
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+//2layer board DDR4
+ .t_pub_acbdlr0 = 0, //0x3f,
+ .t_pub_aclcdlr = 0, //0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0, //0x10,// 0x10,//0xa, //cs add 22ohm 08 0ohm 0x10
+#else // ddr3 and auto
+//4layer ddr3
+ .t_pub_acbdlr0 = 0,
+ .t_pub_aclcdlr = 0,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0,//0xa, //cs
+#endif
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ //tianhe lpddr3 20161013
+ .wr_adj_per = {
+ [0] = 90, //aclcdlr
+ [1] = 100,
+ [2] = 120,
+ [3] = 110,
+ [4] = 120,
+ [5] = 105,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 110,
+ [3] = 110,
+ [4] = 110,
+ [5] = 110,},
+#else
+ /* P212 */
+ .wr_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+ .rd_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=88,
+ [3]=95,
+ [4]=95,
+ [5]=100,
+ },
+#endif
+
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ /* pll ssc setting:
+
+ .ddr_pll_ssc = 0x00120000, ppm1000 center SS, boot log show: Set ddr ssc: ppm1000
+ .ddr_pll_ssc = 0x00124000, ppm1000 up SS, boot log show: Set ddr ssc: ppm1000+
+ .ddr_pll_ssc = 0x00128000, ppm1000 down SS, boot log show: Set ddr ssc: ppm1000-
+
+ .ddr_pll_ssc = 0x00140000, ppm2000 center SS, boot log show: Set ddr ssc: ppm2000
+ .ddr_pll_ssc = 0x00144000, ppm2000 up SS, boot log show: Set ddr ssc: ppm2000+
+ .ddr_pll_ssc = 0x00148000, ppm2000 down SS, boot log show: Set ddr ssc: ppm2000-
+
+ .ddr_pll_ssc = 0x00160000, ppm3000 center SS, boot log show: Set ddr ssc: ppm3000
+ .ddr_pll_ssc = 0x00164000, ppm3000 up SS, boot log show: Set ddr ssc: ppm3000+
+ .ddr_pll_ssc = 0x00168000, ppm3000 down SS, boot log show: Set ddr ssc: ppm3000-
+ */
+ .ddr_pll_ssc = 0,
+};
diff --git a/board/amlogic/gxl_p244_v1/gxl_p244_v1.c b/board/amlogic/gxl_p244_v1/gxl_p244_v1.c
new file mode 100644
index 0000000..d72d5eb
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/gxl_p244_v1.c
@@ -0,0 +1,644 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#include <asm/arch/mailbox.h>
+#ifdef DTB_BIND_KERNEL
+#include "storage.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+ __maybe_unused struct mmc *mmc;
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+#if defined(CONFIG_ENV_IS_NOWHERE) && defined(CONFIG_AML_SD_EMMC)
+ /* try emmc here. */
+ mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ if (!mmc)
+ printf("%s() %d: No MMC found\n", __func__, __LINE__);
+ else if (mmc_init(mmc))
+ printf("%s() %d: MMC init failed\n", __func__, __LINE__);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+#define SAMPLE_BIT_MASK 0xfff
+#define NUM 50
+#define BASE_CH7 1843
+#define P_SAR_ADC_REG0 (volatile unsigned int *)0xc1108680
+#define P_SAR_ADC_CHAN_LIST (volatile unsigned int *)0xc1108684
+#define P_SAR_ADC_REG3 (volatile unsigned int *)0xc110868c
+#define P_SAR_ADC_FIFO_RD (volatile unsigned int *)0xc1108698
+#define P_SAR_ADC_DETECT_IDLE_SW (volatile unsigned int *)0xc11086a4
+#define P_SAR_ADC_REG13 (volatile unsigned int *)0xc11086b4
+#if 0
+#define dbgv(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define dbgv(fmt, ...)
+#endif
+void quicksort1(unsigned int a[], int numsize)
+{
+ int i = 0, j = numsize-1;
+ int val = a[0];
+ if (numsize > 1) {
+ while (i < j) {
+ for (; j > i; j--)
+ if (a[j] < val) {
+ a[i] = a[j];
+ break;
+ }
+ for (; i < j; i++)
+ if (a[i] > val) {
+ a[j] = a[i];
+ break;
+ }
+ }
+ a[i] = val;
+ quicksort1(a, i);
+ quicksort1(a+i+1, numsize-1-i);
+}
+}
+int check_vref(void)
+{
+ int i,count;
+ unsigned int value[50];
+ unsigned int value7=0;
+ unsigned int bak, bak_reg3;
+ unsigned int vref_efuse = (readl(SEC_AO_SEC_SD_CFG12)>>19)&(0x1f);
+
+ if (!vref_efuse) {
+ dbgv("This chip has no FT vref, no need to check, PASS\n");
+ return 0;
+ }
+ //run_command("md 0xc1108680 0x10", 0);
+ dbgv("SEC_AO_SEC_SD_CFG12: 0x%x\n",readl(SEC_AO_SEC_SD_CFG12));
+ dbgv("vref_efuse: %d\n",vref_efuse);
+
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ bak = (readl(P_SAR_ADC_REG13)>>8)&0x3f; /*back up SAR_ADC_REG13[13:8]*/
+ writel((readl(P_SAR_ADC_REG13)&(~(0x3f<<8)))|(vref_efuse<<9), P_SAR_ADC_REG13);
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ writel(0x00000007, P_SAR_ADC_CHAN_LIST);/*ch7*/
+ //writel(0xc000c|(0x7<<23)|(0x7<<7), P_SAR_ADC_DETECT_IDLE_SW);/*channel 7*/
+ bak_reg3 = readl(P_SAR_ADC_REG3);
+ writel((readl(P_SAR_ADC_REG3)&(~(0x7<<23)))|(0x2<<23), P_SAR_ADC_REG3);/*AVDD18/2*/
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ //run_command("md 0xc1108680 0x10", 0);
+ for (i=0;i<NUM;i++) {
+ writel((readl(P_SAR_ADC_REG0)&(~(1<<0))), P_SAR_ADC_REG0);
+ writel((readl(P_SAR_ADC_REG0)|(1<<0)), P_SAR_ADC_REG0);
+ writel((readl(P_SAR_ADC_REG0)|(1<<2)), P_SAR_ADC_REG0);/*start sample*/
+ count = 0;
+ do {
+ udelay(20);
+ count++;
+ } while ((readl(P_SAR_ADC_REG0) & (0x7<<28))
+ && (count < 100));/*finish sample?*/
+ if (count == 100) {
+ printf("%s : ch7 wait finish sample timeout!\n",__func__);
+ return -1;
+ }
+ value[i] = readl(P_SAR_ADC_FIFO_RD); /*read saradc*/
+ if (((value[i]>>12) & 0x7) == 0x7)
+ value[i] = value[i]&SAMPLE_BIT_MASK;
+ else {
+ printf("%s : not ch7! sample err!\n",__func__);
+ return -1;
+ }
+ }
+ quicksort1(value, NUM);
+ for (i = 0; i < NUM; i++)
+ dbgv("%d ", value[i]);
+ dbgv("\n");
+ for (i = 2; i < NUM-2; i++)
+ value7 += value[i];
+ value7 = value7/(NUM-4);
+ dbgv("the average ch7 adc=%d\n", value7);
+ dbgv("vref_efuse: %d\n",vref_efuse);
+ if ((value7 < (BASE_CH7*94/100)) || (value7 > (BASE_CH7*106/100))) { //1843
+ printf("the average ch7 : %d out of range: %d ~ %d\n",
+ value7, (BASE_CH7*94/100), (BASE_CH7*106/100));
+ printf("replace FT vref...\n");
+ thermal_calibration(4, bak>>1); /*[13:9]*/
+ }
+ /*write back SAR_ADC_REG13[13:8]*/
+ writel(((readl(P_SAR_ADC_REG13))&(~(0x3f<<8)))|
+ ((bak & 0x3f)<<8),
+ P_SAR_ADC_REG13);
+ writel(bak_reg3, P_SAR_ADC_REG3);
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ dbgv("SEC_AO_SEC_SD_CFG12: 0x%x\n",readl(SEC_AO_SEC_SD_CFG12));
+ //run_command("md 0xc1108680 0x10", 0);
+ return 0;
+}
+
+int board_late_init(void){
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ ret = check_vref();
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ }
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "gxl_p244_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "gxl_p244_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "gxl_p244_512m\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxl_p244_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/gxl_p244_v1/lcd.c b/board/amlogic/gxl_p244_v1/lcd.c
new file mode 100644
index 0000000..eeaee34
--- a/dev/null
+++ b/board/amlogic/gxl_p244_v1/lcd.c
@@ -0,0 +1,248 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {
+ "lcd_0",LCD_TTL,6,
+ /* basic timing */
+ 1280,720,1650,750,40,220,1,5,20,1,
+ /* clk_attr */
+ 0,0,1,74250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* ttl_attr */
+ 0,1,1,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ 0xff,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+};
+
+//**** Special parameters just for ttl ***//
+static struct ttl_config_s lcd_ttl_config = {
+ .clk_pol = 0,
+ .sync_valid = (1 << 1) | (1 << 0), /* [1]DE, [0]hvsync */
+ .swap_ctrl = (0 << 1) | (0 << 0), /* [1]rb swap, [0]bit swap */
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .ttl_config = &lcd_ttl_config,
+ .lvds_config = &lcd_lvds_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 0,
+ .pinmux_set = {{3, 0x000002a0}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0xfa030000}, {2, 0xf9fe0409}, {3, 0x00000001}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0, //ending flag
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .i2c_bus = LCD_EXTERN_I2C_BUS_D, /* LCD_EXTERN_I2C_BUS_A/B/C/D/AO */
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_on_cnt = sizeof(init_on_table),
+ .table_init_off = init_off_table,
+ .table_init_off_cnt = sizeof(init_off_table),
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinctrl_ver = 0,
+ .pinmux_set = {{2, 0x00000800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0x00000400}, {2, 0x00000020}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
generated by cgit at 2024-05-17 09:07:34 (GMT)